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4.5 / ARM CACHE ORGANIZATION 143

Table 4.5 Pentium 4 Cache Operating Modes

Control Bits Operating Mode
CD NW Cache Fills Write Throughs Invalidates
0 0 Enabled Enabled Enabled
1 0 Disabled Enabled Enabled
1 1 Disabled Disabled Disabled
Note: CD = 0; NW = 1 is an invalid combination.

• Execution units: These units executes micro-operations, fetching the required
data from the L1 data cache and temporarily storing results in registers.
• Memory subsystem: This unit includes the L2 and L3 caches and the system
bus, which is used to access main memory when the L1 and L2 caches have a
cache miss and to access the system I/O resources.
Unlike the organization used in all previous Pentium models, and in most
other processors, the Pentium 4 instruction cache sits between the instruction de-
code logic and the execution core. The reasoning behind this design decision is as
follows: As discussed more fully in Chapter 14, the Pentium process decodes, or
translates, Pentium machine instructions into simple RISC-like instructions called
micro-operations. The use of simple, fixed-length micro-operations enables the use
of superscalar pipelining and scheduling techniques that enhance performance.
However, the Pentium machine instructions are cumbersome to decode; they have a
variable number of bytes and many different options. It turns out that performance
is enhanced if this decoding is done independently of the scheduling and pipelining
logic.We return to this topic in Chapter 14.
The data cache employs a write-back policy: Data are written to main memory
only when they are removed from the cache and there has been an update.The Pen-
tium 4 processor can be dynamically configured to support write-through caching.
The L1 data cache is controlled by two bits in one of the control registers, la-
beled the CD (cache disable) and NW (not write-through) bits (Table 4.5). There
are also two Pentium 4 instructions that can be used to control the data cache:
INVD invalidates (flushes) the internal cache memory and signals the external
cache (if any) to invalidate. WBINVD writes back and invalidates internal cache
and then writes back and invalidates external cache.
Both the L2 and L3 caches are eight-way setassociative with a line size of
128 bytes.

4.5 ARM CACHE ORGANIZATION

The ARM cache organization has evolved with the overall architecture of the ARM
family, reflecting the relentless pursuit of performance that is the driving force for
all microprocessor designers.