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System bus
L3 cache
(1 MB)
bits
64
fetch/decode
Instruction
FP register file
unit
cache (12K ops)
L1 instruction
Simple FP FP/ Complex move MMX integer integer unit unit ALU ALU L2 cache (512 KB) L1 data cache (16 KB) 256 bits
Out-of-order execution logic Integer register file Simple integer ALU
Store address unit Pentium 4 Block Diagram
Load address unit Figure 4.18
142
