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154 CHAPTER 4 / CACHE MEMORY

where
T = average (system) access time
s
T = access time of M1 (e.g., cache, disk cache)
1
T = access time of M2 (e.g., main memory, disk)
2
H = hit ratio (fraction of time reference is found in M1)
Figure 4.2 shows average access time as a function of hit ratio.As can be seen,
for a high percentage of hits, the average total access time is much closer to that of
M1 than M2.

Performance
Let us look at some of the parameters relevant to an assessment of a two-level
memory mechanism. First consider cost.We have
C S + C S
C = 1 1 2 2 (4.3)
s
S + S 2
1
where
C = average cost per bit for the combined two-level memory
s
C = average cost per bit of upper-level memory M1
1
C = average cost per bit of lower-level memory M2
2
S = size of M1
1
S = size of M2
2
We would like C L C . Given that C W C , this requires S V S . Figure
2
1
s
2
2
1
4.22 shows the relationship.
Next, consider access time. For a two-level memory to provide a significant
performance improvement, we need to have T approximately equal to T (T L T ).
1
1
s
s
Given that T is much less than T (T V T ), a hit ratio of close to 1 is needed.
1
2
1
2
So we would like M1 to be small to hold down cost, and large to improve the
hit ratio and therefore the performance. Is there a size of M1 that satisfies both
requirements to a reasonable extent? We can answer this question with a series of
subquestions:
• What value of hit ratio is needed so that T L T ?
1
s
• What size of M1 will assure the needed hit ratio?
• Does this size satisfy the cost requirement?
To get at this, consider the quantity T /T, which is referred to as the access efficiency.
s
1
It is a measure of how close average access time (T) is to M1 access time (T ). From
s
1
Equation (4.2),
T 1 = 1
T s T 2 (4.4)
1 + (1 - H)
T 1
Figure 4.23 plots T /T as a function of the hit ratio H, with the quantity T /T as a pa-
1
2
s
1
rameter.Typically, on-chip cache access time is about 25 to 50 times faster than main