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150 CHAPTER 4 / CACHE MEMORY

4.23 Consider a cache with a line size of 64 bytes.Assume that on average 30% of the lines
in the cache are dirty.A word consists of 8 bytes.
a. Assume there is a 3% miss rate (0.97 hit ratio). Compute the amount of main
memory traffic, in terms of bytes per instruction for both write-through and write-
back policies. Memory is read into cache one line at a time. However, for write
back, a single word can be written from cache to main memory.
b. Repeat part a for a 5% rate.
c. Repeat part a for a 7% rate.
d. What conclusion can you draw from these results?
4.24 On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data
access from main memory over the bus to the processor takes three clock cycles in the
case of no wait state insertion; the data are delivered to the processor in parallel with
delivery to the cache.
a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a
clocking rate of 16.67 MHz.
b. Repeat the calculations assuming insertion of two wait states of one cycle each
per memory cycle.What conclusion can you draw from the results?
4.25 Assume a processor having a memory cycle time of 300 ns and an instruction process-
ing rate of 1 MIPS. On average, each instruction requires one bus memory cycle for
instruction fetch and one for the operand it involves.
a. Calculate the utilization of the bus by the processor.
b. Suppose the processor is equipped with an instruction cache and the associated
hit ratio is 0.5. Determine the impact on bus utilization.
4.26 The performance of a single-level cache system for a read operation can be charac-
terized by the following equation:

T a = T c + (1 - H)T m
where T a is the average access time, T c is the cache access time, T m is the memory ac-
cess time (memory to processor register), and H is the hit ratio. For simplicity, we as-
sume that the word in question is loaded into the cache in parallel with the load to
processor register.This is the same form as Equation (4.2).
a. Define T b = time to transfer a line between cache and main memory, and W =
fraction of write references. Revise the preceding equation to account for writes
as well as reads, using a write-through policy.
b. Define W b as the probability that a line in the cache has been altered. Provide an
equation for T a for the write-back policy.
4.27 For a system with two levels of cache, define T c1 = first-level cache access time; T c2 =
second-level cache access time; T m = memory access time; H 1 = first-level cache hit
ratio; H 2 = combined first/second level cache hit ratio. Provide an equation for T a for
a read operation.
4.28 Assume the following performance characteristics on a cache read miss: one clock
cycle to send an address to main memory and four clock cycles to access a 32-bit word
from main memory and transfer it to the processor and cache.
a. If the cache line size is one word, what is the miss penalty (i.e., additional time re-
quired for a read in the event of a read miss)?
b. What is the miss penalty if the cache line size is four words and a multiple, non-
burst transfer is executed?
c. What is the miss penalty if the cache line size is four words and a transfer is exe-
cuted, with one clock cycle per word transfer?
4.29 For the cache design of the preceding problem, suppose that increasing the line size
from one word to four words results in a decrease of the read miss rate from 3.2% to
1.1%. For both the nonburst transfer and the burst transfer case, what is the average
miss penalty, averaged over all reads, for the two different line sizes?