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40 CHAPTER 2 / COMPUTER EVOLUTION AND PERFORMANCE

In fact, instructions are scheduled to be executed when ready, independent of
the original program order.This prevents unnecessary delay.
• Speculative execution: Using branch prediction and data flow analysis, some
processors speculatively execute instructions ahead of their actual appearance
in the program execution, holding the results in temporary locations. This en-
ables the processor to keep its execution engines as busy as possible by exe-
cuting instructions that are likely to be needed.

These and other sophisticated techniques are made necessary by the sheer power
of the processor.They make it possible to exploit the raw speed of the processor.

Performance Balance
While processor power has raced ahead at breakneck speed, other critical compo-
nents of the computer have not kept up.The result is a need to look for performance
balance: an adjusting of the organization and architecture to compensate for the
mismatch among the capabilities of the various components.
Nowhere is the problem created by such mismatches more critical than in the
interface between processor and main memory. Consider the history depicted in
Figure 2.10.While processor speed has grown rapidly, the speed with which data can
be transferred between main memory and the processor has lagged badly.The inter-
face between processor and main memory is the most crucial pathway in the entire
computer because it is responsible for carrying a constant flow of program instruc-
tions and data between memory chips and the processor. If memory or the pathway
fails to keep pace with the processor’s insistent demands, the processor stalls in a
wait state, and valuable processing time is lost.

MHz
3500
Logic
3000

2500

2000

1500

1000
Memory

500

1992 1994 1996 1998 2000 2002
Figure 2.10 Logic and Memory Performance Gap [BORK03]