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2.2 / DESIGNING FOR PERFORMANCE 41

There are a number of ways that a system architect can attack this problem, all
of which are reflected in contemporary computer designs. Consider the following
examples:
• Increase the number of bits that are retrieved at one time by making DRAMs
“wider” rather than “deeper” and by using wide bus data paths.
• Change the DRAM interface to make it more efficient by including a cache 7
or other buffering scheme on the DRAM chip.
• Reduce the frequency of memory access by incorporating increasingly com-
plex and efficient cache structures between the processor and main memory.
This includes the incorporation of one or more caches on the processor chip as
well as on an off-chip cache close to the processor chip.
• Increase the interconnect bandwidth between processors and memory by
using higher-speed buses and by using a hierarchy of buses to buffer and struc-
ture data flow.

Another area of design focus is the handling of I/O devices. As computers be-
come faster and more capable, more sophisticated applications are developed that
support the use of peripherals with intensive I/O demands. Figure 2.11 gives some

Gigabit Ethernet

Graphics display

Hard disk
Ethernet

Optical disk
Scanner

Laser printer
Floppy disk

Modem

Mouse
Keyboard
10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9
Data rate (bps)
Figure 2.11 Typical I/O Device Data Rates`

7 A cache is a relatively small fast memory interposed between a larger, slower memory and the logic that
accesses the larger memory. The cache holds recently accessed data, and is designed to speed up subse-
quent access to the same data. Caches are discussed in Chapter 4.