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72 CHAPTER 3 / A TOP-LEVEL VIEW OF COMPUTER FUNCTION

address 941 and stores the result in the latter location.Three instructions, which can
be described as three fetch and three execute cycles, are required:
1. The PC contains 300, the address of the first instruction. This instruction (the
value 1940 in hexadecimal) is loaded into the instruction register IR and the
PC is incremented. Note that this process involves the use of a memory ad-
dress register (MAR) and a memory buffer register (MBR). For simplicity,
these intermediate registers are ignored.
2. The first 4 bits (first hexadecimal digit) in the IR indicate that the AC is to be
loaded. The remaining 12 bits (three hexadecimal digits) specify the address
(940) from which data are to be loaded.
3. The next instruction (5941) is fetched from location 301 and the PC is
incremented.
4. The old contents of the AC and the contents of location 941 are added and the
result is stored in the AC.
5. The next instruction (2941) is fetched from location 302 and the PC is
incremented.
6. The contents of the AC are stored in location 941.
In this example, three instruction cycles, each consisting of a fetch cycle and an
execute cycle, are needed to add the contents of location 940 to the contents of 941.
With a more complex set of instructions, fewer cycles would be needed. Some older
processors, for example, included instructions that contain more than one memory
address. Thus the execution cycle for a particular instruction on such processors
could involve more than one reference to memory. Also, instead of memory refer-
ences, an instruction may specify an I/O operation.
For example, the PDP-11 processor includes an instruction, expressed symbol-
ically as ADD B,A, that stores the sum of the contents of memory locations B and A
into memory location A. A single instruction cycle with the following steps occurs:
• Fetch the ADD instruction.
• Read the contents of memory location A into the processor.
• Read the contents of memory location B into the processor. In order that the
contents of A are not lost, the processor must have at least two registers for
storing memory values, rather than a single accumulator.
• Add the two values.
• Write the result from the processor to memory location A.

Thus, the execution cycle for a particular instruction may involve more than
one reference to memory. Also, instead of memory references, an instruction may
specify an I/O operation. With these additional considerations in mind, Figure 3.6
provides a more detailed look at the basic instruction cycle of Figure 3.3.The figure is
in the form of a state diagram. For any given instruction cycle, some states may be
null and others may be visited more than once.The states can be described as follows:

• Instruction address calculation (iac): Determine the address of the next in-
struction to be executed. Usually, this involves adding a fixed number to the