Page 106 - DSP Integrated Circuits

3.16 FFT—The Fast Fourier Transform Algorithm 91

Figure 3.24 Butterfly for decimation-in-time

Note that one of the multiplications can be eliminated by a simple modifica-
tion of the butterfly. Due to its appearance this flow graph is called a butterfly.
Most hardware implementations of the FFT are based on one or several processors
that implement the butterfly operations. Today, the DFT plays an important role
as a building block in many digital signal processing systems. Both special pur-
pose hardware and processors have been developed in order to facilitate real-time
signal processing. Typically, a complex sequence of length N = 1024 can be trans-
formed in 1 to 5 ms using standard signal processors.
Table 3.1 shows benchmarks for some standard signal processors. Note that
the benchmarks do not include time for input and output of the sequences and
that they may be measured under slightly different conditions and that processors
with different clock frequencies are available.

Company Model Description 1024-point FFT [ms]
Analog Devices ADSP-2101 16/40-bit fixed-point 2.26
ADSP-2120 32-bit floating-point 0.77
ADSP-21020 32-bit floating-point 0.58
AT&T DSP32C 32-bit floating-point 2.9

Motorola DSP56002 24-bit fixed-point 4
DSP96002 32-bit floating-point 1.13

Texas Instruments TMS320C25 16-bit fixed-point 15.9
TMS320C30 32-bit floating-point 3.0
TMS320C40 32-bit floating-point 1.0
Table 3.1 Benchmarks for standard signal processors

Table 3.2 shows benchmarks for a few commercial FFT processors. These high-
performance processors generally require several support chips, (for example,