Page 107 - DSP Integrated Circuits

92 Chapter 3 Digital Signal Processing

external memory) to perform the FFT. Special-purpose hardware can reduce the
execution time by more than an order of magnitude.

1024-point FFT
Company Model Description [fis]
Plessey PDSP16510A 16-bit block floating-point 98
Array Microsystems DaSP Chip set Processor and Controller 130
Butterfly DSP Inc. BDSP9124 24-bit fixed-point 54
France Telecom. CNET FT-VD-FFT8K-4 12-bit block floating-point 52
Sharp LH9124L 24-bit fixed-point 129
LH9320LU-25
Table 3.2 Benchmarks for some FFT processors

EXAMPLE 3.6
Derive the Cooley-Tukey FFT (i.e., the decimation-in-time algorithm), for N = 4.
Hint: Use the following binary representations:

and

where ki, k$, n-^, and HQ are either 0 or 1.
The DFT is

Using this notation and noting that the sum over the time index, n, can be
written as a double sum over n\ and n$

X(ki, k Q) = jc 0(ni, n 0) W nk
with

4k n
Since W i i = 1, we get

Let Xi(&o> no) denote the inner sum, i.e.,

or, more explicitly,