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3.20 DCT Processor—Case Study 2 105

Figure 3.32 Fast even IDCT algorithm

DCTs. The number of real multiplications and additions (subtractions) for the fast
DCT/IDCT are 0.5Anog 2(AO and 1.5N\og 2(N)-N+l, respectively. Figure 3.32 shows
m
the signal-flow graph for the even IDCT [28] for N = 2 = 8 where

Note that the input is in bit-reversed order. A fast DCT algorithm can be
derived by transposing the signal-flow graph shown in Figure 3.32, i.e., reversing
the directions of all branches.
In 1991, a fast algorithm for the 2-D even DCT was proposed by Cho and Lee
2
[13]. The algorithm is regular and modular and requires only 0.5A/" log2(AO multi-
2
plications and 2.5N log2(N)-2N+2 additions.

3.20 DCT PROCESSOR—CASE STUDY 2

As the second case study we select a two-dimensional DCT processor intended for
use in a future transform coding system for real-time image processing [1,27 30, 37,
38]. The processor is assumed to be a part of a larger integrated circuit and in this
study we therefore neglect the I/O aspects of the processor. The throughput require-
ment for such a DCT processor varies considerably between different transform cod-
ing schemes and applications. Currently there is no standard established for HDTV.