Page 123 - DSP Integrated Circuits

108 Chapter 3 Digital Signal Processing

additions would be increased to 23. The required number of arithmetic operations
per second for the 2-D DCTs is
6
486,000 • (16 + 16) • 16 = 248.8 10 Mult/s
and
6
486,000 • (16 + 16) • 15 = 233.3 10 Add/s
Now, most standard signal processors are designed to perform a multiplica-
tion and an addition concurrently. Hence, an algorithm with a poor balance
between the number of multiplications and number of additions will be inefficient.
We therefore decide to use a direct computation of the DCTs. The transposition of
the intermediate array adds a significant number of operations for address calcu-
lations in addition to overhead for I/O, etc. Hence, this work load is much too high
for today's standard digital signal processors. However, the number of operations
is reduced if a fast DCT algorithm is used, but even in this case the work load will
be too large.

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