Page 121 - DSP Integrated Circuits

106 Chapter 3 Digital Signal Processing

One of the candidates is called CIL (common image lattice). The main parame-
ters for the CIL system are shown in Table 3.3. The color signals (R, G, and B) are
mapped linearly to a luminance (Y) and two chrominance signals (U and V). The dis-
crete cosine transform is computed for these signals individually. Table 3.4 shows
the main performance characteristics of some recently published DCT designs.

Field frequency [Hz] 60 50
Active lines/frame 1080 1152
Samples/active line 1920 2048
Sample frequency 74.25 74.25
Total number of lines 1125 1250
Samples/line 2200 2376
Scanning algorithm 2:1 2:1
Bits/sample 8 8
Gross bit rate [Mbit/s] 1188 1188
Active bit rate [Mbit/s] 995.3 943.72
Pixels/s [MHz] 124.4 118
16 x 16 DCTs/s 486000 461000
Table 3.3: Parameters for the CIL HDTV system

Most designs today are based on an 8 x 8 point DCT due to the stringent
requirements. The required number of 8 x 8 DCTs/s for the most stringent HDTV
6
requirement with the largest screen size is about 1.95 10 . Obviously, none of the
designs meet the requirements for HDTV, but they are usable for smaller screen
sizes. However, using a modern CMOS process with smaller geometries, the
throughput requirements can be met.

Company, etc. Model Algorithm Description
SGS Thomson STV 3200 8 x 8 even DCT 1.2-um CMOS
27 Mpixel/s Serial-parallel multipliers

SGS Thomson STV 3208 8 x 8 even DCT 1.2-jun CMOS
27 Mpixel/s Serial-parallel multipliers
Jutand et al. [26] — 8x8 even DCT 0.8-^im CMOS
Fast algorithm Active chip area = 41 mm 2
72 Mpixel/s 16-bit data and coefficient word lengths
Jutand et al. [26] — 8x8 even DCT 0.8-um CMOS
Distributed arithmetic Active chip area = 41.4 mm 2
72 Mpixel/s 16-bit data and 10-bit coefficient word
lengths

Defilippis [18] — 16 x 16 MSDCT 2 \un CMOS
Distributed arithmetic Active chip area = 22.5 mm 2
100 Mpixel/s 16-bit data and 10-bit coefficient word
lengths

Chau[ll] — 8x8 even DCT 0.8-|im BiCMOS gate array
Distributed arithmetic 21.6 mm 2
100 Mpixel/s < 2.2 W
16-bit data word length
Table 3.4 Benchmarks for some ASIC DCT processors