Page 205 - DSP Integrated Circuits

190 Chapter 5 Finite Word Length Effects

Figure 5.2 Zero-input limit cycles resulting from rounding and truncation of the
products. The outputs have been multiplied by 1/Q = 512 in order to show the
parasitic oscillations more clearly.

The quantization errors resulting from truncating the two's-complement num-
bers have a negative average value Q/2 which will appear as a DC offset at the
output. The offset will be large if the DC gain measured from the quantization
node to the output of the filter is large. In this filter the DC gain is

The average output signal is therefore 18.285Q.

The zero-input case is in many respects the simplest case and extensive
research efforts have been directed toward the problem of eliminating zero-input
limit cycles in first- and second-order sections. Zero-input limit cycles can in some
second-order structures be eliminated for certain pole positions [2]. Several elabo-
rate data-dependent quantization schemes (e.g., controlled rounding [24]) have
also been proposed. Another special class of oscillation, which is not so simple to