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280 Chapter 7 DSP System Design

7. In the next step, the resource assignment step, the operations are
assigned to specific PEs and the results of the operations are assigned to
specific memories and memory cells. The transactions between PEs and
memories are assigned to appropriate communication channels. The
methods we will use are based either on clique partitioning or on the left-
edge algorithm used for optimizing memory utilization. The left-edge
algorithm is a well-known algorithm used for wire routing.
In this step, we minimize the cost of the PEs, memories, and
communication circuitry. In Chapter 9 we will show that it is advantageous
to use specialized bit-serial PEs and bit-parallel RAMs for data storage.
The bit-serial PEs must therefore communicate with the memories through
serial-parallel converters that act as cache memories.
8. The next step involves logic design of the modules in the architecture—
i.e., the PEs, memories, control units, etc. Control signals, which are also
derived from the schedule, are defined in this step.
9. In the circuit design step, the modules are designed at the transistor
level. Transistor sizes are optimized with respect to performance in terms
of speed, power consumption, and chip area.
10. The last step, the VLSI design phase, involves layout—i.e., floor planning,
placement, and wire routing. A key concept is that neither system nor
circuit design is done in this phase.

The scheduling, resource allocation, and assignment problems are, in general,
NP-complete problems. They are therefore, in practice, solved in sequence and the
whole design sequence, steps 3 through 9, must be iterated until a satisfactory
solution is found.
We stress that design is an iterative process. We can not expect to go through
the preceding steps only once. Instead, we must be prepared to redesign the sys-
tem at a higher level if the lower levels reveal nonsolvable problems or lead to an
inefficient solution. The estimate of system parameters (e.g., chip area or power
consumption) will become more and more accurate as design progresses. In the
first pass through a design level we may do a preliminary, crude design and suc-
cessively refine it in subsequent design iterations. Generally, we are also inter-
ested in exploring the design space by investigating a large variety of design
alternatives. Simulation and other means of validation are required to validate
and evaluate the design decisions at all levels.
However, these design steps are highly interdependent. For example, the cost
function that is minimized by the scheduling assumes certain costs for communi-
cation, PEs, and memories. Further, the selection of a particular algorithm
restricts the class of usable architectures. Therefore, the synthesis process must,
in practice, be followed by an evaluation phase and a subsequent design iteration.
The design process may need to be reiterated several times in order to achieve a
satisfactory solution. It may also require extension to a lower level of abstraction
in order to improve the performance of the hardware components.

7.3 FFT PROCESSOR, CONT.

In this chapter we will perform the main steps in the system design phase of the
FFT processor. This means that we will synthesize the architecture with its hard-