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472                                            Chapter 11 Processing Elements


        RNS number it has to be converted to a normal number representation. RNS is
        therefore not suitable for use in recursive loops. Division is possible only in special
        cases and would seriously complicate the system. Further, the dynamic range
        must then be kept under strict control. Overflow would spoil the results. The RNS
        method is effective only for special applications— e.g., nonrecursive algorithms.




        11.5    BIT-PARALLEL ARITHMETIC


                                            "Heigh-ho, Heigh-ho, it's off to work we go...
                                                    Larry Morey and Frank Churchill

        In this section we will discuss methods to implement
        arithmetic operations such as addition, subtraction,
        and multiplication using bit-parallel methods. These
        operations are simple to implement in two's-comple-  Figure 11.2 Full-adder
        ment representation, since they are independent of
        the signs of the numbers involved. Hence, two's-com-
        plement representation is used predominantly. However, in many cases it is
        advantageous to exploit other number systems to improve the speed and reduce
        the required chip area and power consumption.
            The basic computation element for addition, subtraction, and multiplication is a
        full-adder (FA). It accepts three binary inputs: A, B, and D, called addend, augend,
        and carry-in, respectively. The two outputs are the sum, S, and the carry-out, C. A
        symbol for the full-adder is shown in Figure 11.2. We have for the full-adder







            These expressions can be modified to be more suitable for implementation in
        CMOS with XOR gates:












        11.5.1 Addition and Subtraction

                                        x
        Two binary numbers, x = Oco«#i*2--- Wd-l) andy = (yo<yiy2--- ywd-l\  can  be added
        bit-serial in O(W^) steps and, by using more advanced techniques and bit-parallel
        operation, the number of steps, or gate levels, can be reduced to only O(log(W^)).
        Notice, however, that the times required for a computational step may differ
        between different addition algorithms, since the switching time also depends on
        gate loads. In practice the addition time for one algorithm with more steps may
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