Page 490 - DSP Integrated Circuits

11.5 Bit-Parallel Arithmetic 475

the sum bits of the last block. The carry propagation path is through the carry skip
circuitry and the final RCA. The addition time is O(JW d). The Manchester adder
is a special case of carry-skip adder. A carry-skip adder usually requires less chip
area than the corresponding CSA; however, it can not be pipelined.

Conditional-Sum Adder
The conditional-sum adder generates all possible sums and carries in a manner
similar to the carry-select adder [22]. The conditional-sum adder uses a modified
half-adder to generate sums and carries in the first phase. The second phase uses
log2(W^) levels of multiplexers to conditionally combine neighboring bits into the
final sum [36]. This adder can easily be pipelined by placing latches after the first
phase and after every multiplexer stage. The conditional-sum adder, implemented
using dynamic CMOS circuits [25], is usually faster than a carry-look-ahead
adder, but both adders have complex interconnections that require large chip
areas. The conditional-sum adder should be considered as a candidate for high-
speed CMOS adders.

11.5.2 Bit-Parallel Multiplication
In order to multiply two two's-complement numbers, a and x, we form the partial
bit-products aj • Xk, as shown next in Figure 11.5. High-speed, bit-parallel multipli-
ers can be divided in three classes [19, 27]. The first type, so-called shift-and-add
multipliers, generates partial bit-products sequentially and accumulates them
successively as they are generated. This type is therefore the slowest multiplier,
but the required chip area is low.
The second type generates all bit-products in parallel and uses a multi-oper-
and adder (i.e., an adder tree) for their accumulation. This multiplier type is also
known as parallel multiplier. A parallel multiplier structure can be partitioned
into three parts: partial product generation, carry-free addition, and carry-propa-
gation addition. These three parts can be implemented using different schemes.
For example, the partial product generation can be implemented by AND gates or
by using the Booth's algorithm, as described in section 11.5.4. The carry-free addi-
tion part is often implemented by using a Wallace or redundant binary addition
tree. The last part can employ one of the addition schemes just described.
Finally, the third type of multipliers uses an array of almost identical cells for
generation of the bit-products and accumulation. This type of multipliers is called

Figure 11.5 Bit-products used in multiplication