Page 489 - DSP Integrated Circuits

474 Chapter 11 Processing Elements

The CLA exploits the fact that the carry generated by a bit-position depends
on the three inputs to that position. If xi = yi = 1, a carry is generated indepen-
dently of the carry from the previous bit-position and if jcj =yi = 0, no carry is gen-
erated. If xi ^ y>i, a carry is generated if and only if the previous bit-position
generates a carry. It is possible to compute all the carries with only two gate
delays (although this would require gates with excessive fan-in). The fan-in of
logic gates increases linearly with the number of bits in the adder. The high fan-in
forces the CLA to be partitioned into blocks with carry-look-ahead. The block size
is usually selected in the range three to five.
A 1992 comparison among adders [8] shows that the CLA adder, which also is
amenable to pipelining, is one of the fastest adders. The implementation of a CLA
adder, using dynamic CMOS logic, was reported in 1991 [41].

Carry-Save Adder
Carry—save adders are suitable when three or more operands are to be added, as
in some multiplication schemes [22]. In this adder a separate sum and carry bits
are generated for the partial results, except when the last operand is added. For
example, if three numbers are to be added, the first two are added using a carry-
save adder. The partial result is two numbers corresponding to the sum and the
carry. The last operand is added using a second carry-save adder stage. The result
becomes a sum and carry number. Thus, a carry-save adder reduces the number of
operands by one for each adder stage. Finally, the sum and carry numbers are
added using an adder with carry propagation—for example, carry-look-ahead
adder.

Carry-Select Adder
Carry-select adders (CSAs) and carry-skip adders provide a compromise between
RCA and CLA adders. The carry—select adder is based on precomputation of some
partial results for the two possible values of the carry bits and using the carry
from the previous bit-position to select the proper result [3].
The CSA adder is for complexity reasons also divided into blocks of RCAs. The
carry into the first block is known, but the carries into the rest of the blocks are
unknown. Now, 0 and 1 are the only possible carries into a block and the two possi-
ble sums and carries out from each block can therefore be computed. Next, the
carry from the previous block selects the correct sum and carry-out, which in turn
select the next blocks sum and carry-out, until the last sum and is selected.

Carry-Skip Adder
The carry-skip adder is also divided into RCA blocks [22]. The first block has no
input carry while the carry into a subsequent block is generated by the skip circuit
of the previous block. As in the CSA, all blocks receive the inputs simultaneously.
The basic principle is that a carry will be propagated, by the blocks skip circuit,
only if all of the inputs to the block are in the propagate state; otherwise a 0 or 1
carry will generated [9, 43]. If a block is in the propagate state, then the carry-out
is the same as the carry into the block. Hence, the carry skips over the block. On
the other hand, if the block is in a nonpropagate state, then the carry-out of the
block is determined by the blocks inputs only.
The sum bits in a block must be computed with the proper input carry. These
computations, for all but the last block, can be overlapped with the computation of