Page 494 - DSP Integrated Circuits

11.5 Bit-Parallel Arithmetic 479

Several alternative addition
schemes are possible. For exam-
Inputs to the
ple, Dadda has derived a scheme
second stage
where all bit-products with the
same weight are collected and Result of the
added using a Wallace tree with second stage
a minimum number of counters
and minimal critical paths.
However, the multiplier is irreg-
ular and difficult to implement
Inputs to the
efficiently since a large wiring
third stage
area is required. Wallace tree
multipliers should therefore only
Result of the
be used for large word length third stage
and where the performance is
Figure 11.10 Reduction of the number of partial
critical.
products
11.5.6 Array Multipliers

Many array multiplier schemes have been proposed. Varying degrees of pipelining
are used, ranging from nonpipelined to fully systolic or wave front arrays. In this
section we will only discuss a typical array multiplier—the Baugh-Wooley's multi-
plier with a multiplication time proportional to 2W^.
The Baugh-Wooley's multiplier scheme can be derived as follows:

Each of the two negative terms may be rewritten

and by using the overflow property of two's-complement representation we get

We get