Page 499 - DSP Integrated Circuits

484 Chapter 11 Processing Elements

EXAMPLE 11.6
Show that subtraction of the bit-products required for the sign-bit in the serial/par-
allel multiplier can be avoided by extending the input by W c-l copies of the sign-bit.
After Wrf— 1 clock cycles the most significant part of the product is stored in the
D flip-flops. In the next W c clock cycles the sign bit of x is applied to the multipliers
input. This is accomplished by the sign extension-circuit shown in Figure 11.15.
The sign extension-circuit consists of a latch that transmits all bits up to the sign-
bit and thereafter latches the sign-bit. For simplicity, we assume that W^ = 6 bits
and W c = 5 bits.

Figure 11.15 Serial/parallel multiplier with sign-extension circuit

The product is

but the multiplier computes

The first term here contributes an error in the desired product. However, as
shown next, there will not be an error in the Wd+W c—l least-significant bits since
the error term only contributes to the bit positions with higher significance.

A bit-serial multiplication takes at least W^+W C— 1 clock cycles. In section
11.15, we will present a technique that uses partially overlapping of subsequent