Page 497 - DSP Integrated Circuits

482 Chapter 11 Processing Elements

of power. Power-efficient realization of the clocked elements is therefore impor-
tant. To summarize, bit-parallel and bit-serial arithmetics each have their advan-
tages and disadvantages.

11.6.1 Bit-Serial Addition and Subtraction

In bit-serial arithmetic the numbers are normally processed with the least-signifi-
cant bit first. Bit-serial numbers in a two's-complement representation can be
added or subtracted with the circuits shown in Figure 11.13.
Since the carries are
saved from one bit position to
the next the circuits are
called carry-save adder and
carry-save subtracter, respec-
tively. At the start of the
computation the D flip-flop
is reset (set) for the adder
(subtracter), respectively. Figure 11.13 Bit-serial adder and subtracter
We have for addition

and for subtraction:

11.6.2 Bit-Serial Multiplication
According to Figure 11.5, the multiplication of two two's-complement numbers, y =
a • x, requires the formation of the partial bit-products by multiplying the coeffi-
cient, a, by the bits of x. The partial products can then be added bit-serially with
the proper weighting. This addition can be performed by a variety of schemes. The
slowest bit-serial multipliers are obtained if only one bit-product is generated and
added in each time slot. Most bit-serial multipliers, however, are in practice based
on the shift-and-add algorithm where several bit-products are added in each time
slot. We will describe several such bit-serial multipliers in the next sections.

11.6.3 Serial/Parallel Multiplier

Many forms of so-called serial/parallel multipliers are have been proposed [24,37].
In a serial/parallel multiplier the multiplicand, x, arrives bit-serially while the