Page 186 - Embedded Microprocessor Systems Real World Design

face that can be used to communicate between two DSPs. In this system, which
is a simplified diagram of an actual design, both DSPs had to service a regular,
high-priority interrupt every few microseconds. DSPl controlled some high-speed
(proprietary) circuitry. DSP2 processed the output from that circuitry and com-
municated with a host processor on another board. The two DSPs communicated
via the serial link, sending 16 bits of data at a time.
I wanted to use the high-speed serial link for interprocessor communication, but
processing the regular interrupt could not be delayed more than a few clock cycles.
Since the ADSP-2101 has only one alternate register set, which I already was using,
I did not want to use nested interrupts. The normal method of servicing the receive
interrupt would be to read the word from the input register, check for errors, put
the received word in a buffer, and then return. I could not afford to delay this long
before servicing the regular interrupt.
One detail about the design that made the problem solvable was that the serial
interface was not receiving or sending a continuous stream of data. Information
was sent over the serial link intermittently. The solution was to add an edge-
sensitive acknowledge interrupt from DSPl to DSP2 and vice versa. When a byte is
received by DSP2 from DSP1, the receive interrupt code just sets a flag and returns.
The polling loop checks the flag once per pass, and if data are available, it reads
and processes the received word.
The acknowledge interrupt is used to prevent data overruns if DSPl wants to
send more than one word. When DSPl transmits, it clears a semaphore, TXRDY.
It will not transmit again until TXRDY is set, which happens when DSP2 sends back
the interrupt. DSP2 does this when it has processed a received byte. If the polling
loop gets busy processing host data and does not get to the received byte, DSPl just
waits. If necessary, the FIFO buffer can continue to fill with pending transmit data,
although this rarely occurred in the actual system.
Since the acknowledge interrupt and receive interrupt merely set flags, they
need not save any registers. The ISRs consist of two instructions: one to set the flag
and an interrupt return. The pseudocode for the polling loop and interrupts
follows (DSP2 is shown; DSPl is the same without the host processing part):

start of polling loop:
If RXRDY is set (Rx serial data available),
Read data byte
Send acknowledge interrupt to DSPl
Process Rx data.
If host data available,
Read host data
Process host data.
If transmit data available for DSPl ,
Write data to transmit FIFO buffer.

Intmpts in Embedded Systems 167