Page 380 - Embedded Microprocessor Systems Real World Design
P. 380

State machine (s)                    Timing
                   description of, 129-130              access
                   incremental, 130                      for EPROM, 42
                   multiple, 130                         for RAM, 4548
                 STD bus, 265                           acknowledge, 2 25-226
                 Stress testing of system, 19G-197      calculations, 54
                 Strobes                                cumulative errors and, 163-164,  227-228
                   data, 62                             DMA, 79-80,  80f
                   read, 48, 49f, 54                    DRAM, 49-50,51f
                  write, 48, 49f                        interrupt effects, 156
                 Superloop. see Polling loop(s)         Microwire, 71f
                 Switch closure, 138                    schematic representation of, 43f
                 Switch debouncing, 169                 SDRAM, 276
                 Synchronization                        of  software, 177
                   of distributed processor systems, 24   Timing logic
                  of multiprocessor systems, 226       description of, 328
                                                       functions of, 337
                 Task control block, 242              Toshiba
                 Tasks, in real-time operating system. see also   TC59LM814,53
                      Multitasking                     TH50VSF0302, 100
                  communication between, 243-244      Trace data, for debugging
                  scheduling of, 244                   circular trace buffers creating, 178-179
                  tracking of, 242                     read from ROM, 176177
                 Task switch, 250                      software timing and, 177
                 Test specifications, 1               Transceiver, 320
                 Timer                                Tristate, 106, 319
                  counters                            True/false notation, 319
                    count ambiguity considerations, 114
                    description of, 109-1 11          UART  (universal asynchronous
                  description of, 107                      receiver/transmitters)  , 59, 67-68, 77,
                  design considerations for, 115           78f, 169, 183
                  ICs, 58                             Update rate, 4
                  input capture, 109-110
                  interrupts caused by,  147, 153, 154f,   Vector. see Interrupt vectors
                        163-164,  178                VME bus, 267
                  motor control, 113-1  14           von Neumann architecture, 14-15,  15f
                  for pool pump timer system example,
                        300f-301f                    Wait On, 248
                  PWM, 110, 114                      Wait states
                  in real-time operating system, 246   bus types and, 36-38
                  reloading, l08f, 109                 description of, 35-36,63
                  schematic diagram of, 108f           dual-port RAM and, 212
                  temperature measurements, 11  1-1 13   extended data hold time and, 65
                  watchdog                             flash memory and, 277
                    description of, 81                 integral generators, 36
                    electrostatic discharge protection sec-   internal, 36
                       ondary to, 88                   peripheral needing, 37
                    functions of, 81-82                timing of, 34, 36
                    mechanism of operation, 82, 83f   Watchdog timer
                    sophisticated types of, 82         built-in, 82
                Timer code, 120                        description of, 81
                Time slicing                           electrostatic discharge protection sec-
                  definition of, 238                        ondary to, 88
                  sequential scheduling and, 239       functions of, 81-82


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