Page 376 - Embedded Microprocessor Systems Real World Design

components of, 32-33 reasons for using, 203
data bus, 69, 70f schematic representation of, 204f,
RF energy, 86-87 204205
singlechip design and, comparison Multitasking
between, 30f, 31-35 definition of, 238
Multiple buses, 277-278 eventdriven scheduling, 240-241
Multiple-instruction fetch, 280-281 preemptive scheduling, 239, 241, 251
Multiplexer, 320 tasks activation and deactivation, 239-240
Multiplexing time slicing and, 238, 239f
address bus, 35f, 41
description of, 33 NAND gate, 316, 317f
input, 92 Nested interrupts, 146, 157-158, 178
Multiprocessor systems. see also Distributed Noise, 127
processor systems Nonmasking interrupts, 150
acknowledge timing, 225-226 Nonvolatile memory, 70-71
code complexity for, 205 Nonvolatile storage, 14
design pitfalls for NOR gate, 316, 317f
berserk processors, 227 Normally-not-ready bus, 36-37
cumulative time errors, 227-228 Number systems
error handling, 227 binary numbers, 306-308
isolation, 228 computer representation of numbers,
locking problems, 228-232 308-310
multiple measurements, 226 converting numbers between bases,
revisions, 227 306-307
synchronization, 226 floating point, 311-313
dual-port RAM hex numbers, 306-308
data corruption, 216, 228 negative numbers, 308-310
data transfer methods, 215 number bases, 303-306
drawbacks to, 215 suffixes, 310-311
guidelines for using, 229-230 NVRAM. 45
mechanism of operation, 212
schematic representation of, 213f On-chip debug, 282-284
semaphore use, 215-216 One-time programmable devices, 12, 39
engineering specifications, 232-233 Opcodes, 329
interprocessor communication methods Open-collector, 221, 316
asynchronous serial interface, 218 Open drain, 316
asynchronous serial port, 221, Operator training/competence, for micro-
222f-223f processor, 17
CAN bus, 218-220, 220f Optimizing compiler, 133, 162
FIFO buffers, 211-212 OR gate, 316, 31’7f
message stackup problems, 212 Oscillators. see also Clock(s)
opencollector serial interface, 221 crystal, 90, 91f
parallel port interface, 221-224 external, 92
for processors on different boards, 218 Pierce, 90, 92
registers Output contention, 316
with DMA-controlled transfers, Output enable time, 44
207-21 1
fast/slow communication problems, Page mode, of DRAM, 273-274, 274f
210-211,211f Parallel port interface, for interprocessor
with flip-flop status, 206-207, 207f communication in multiprocessor
with interrupt input, 207 systems, 221-224
principles of use, 205-21 1 Partitioning
serial communication, 216-218 code, 125-129
overview of, 203-204 hardware, 22-24

Index 357