Page 373 - Embedded Microprocessor Systems Real World Design

electrically erasable. see EEPROM Hardware
erasing process, 41 memory management, 284-286
inputs for, 4142 partitioning determinations, 22-24
memory, 38-39 requirements estimations, 20-22
output enable time, 44 specifications, 1, 20-22,25, 115-117
schematic representation of, 38f Harvard architecture, 14-15, 15f
Erasable programmable read-only memory. H-bridge, 127
seeEPROM Hex numbers, 306-308
ESD High-level language, 131-135, 341
definition of, 87
protection methods, 88 I‘C bus
Eventdriven scheduling, 240-241 buffering of, 217-218
Exception characteristics of, 71-72
definition of, 286 development of, 72
handling of, 286 for interprocessor communication in
multiprocessor systems, 217-218
Failure mode effects analysis, 197 Microwire and, comparisons between, 74t
Fast cycle termination, 95-96 schematic representation of, 71f, 71-72
Field programmable gate array, 281 speed of, 72
FIFO buffers, 211-212 ICs
Filters, for electrostatic discharge protec- combination, 100-101
tion, 88 controller, 53-54
Firmware specifications, 1 description of, 58
Flash memory. see also EPROM functions, 59-63
access time calculations, 42-45 interface, 59
advantages of, 39 peripheral. see Peripheral ICs
block-organized, 40 RAM, 65
device manufacturer identification by, 40 ROM, 65
erasing of, 39-40 SDRAM, 276
incircuit programming of, 39-40, 83-84 self-refresh capability, 53
mechanism of operation, 40 timer, 58
programming of, 40-41 Idle loop. see Polling loop (s)
properties of, 39 In-circuit programming
SRAM and, 100 description of, 14, 83
wait states and, 277 of flash memory, 39-40, 83-84
Flipflop schematic representation of, 84f
“D,” 106-107 Incremental state machine, 130
registers with, 206207, 207f Input capture registers, 113
set/reset, 320 Input capture timer, 109-110
Floating-point calculations, 133, 31 1-313 Instruction set, evaluation of, 11-12
Flowcharts Integrated circuits. see ICs
description of, 123 Intel
for pool pump timer system example, 80186, 65
297f-299f 80188
Flyby transfer, 79 description of, 60-61
FPGA, 281 interfaces, 65
Functional requirements, 1 8OC96OSA, 65
i960 VH processor, 98, 277-278
Gating logic, 67f timing for, 32-33
Grounding, for electrostatic discharge pro- Interfaces
tection, 88 built-in, 99-1 00
Ground loops, 88 description of, 67
differential, 88-89
Hard deadlines, 138 DRAM, 99-100

354 Index