Page 369 - Embedded Microprocessor Systems Real World Design

Index

Page numbers followed by “t” denote tables; those followed by “f‘ denote figures

Access time reference voltage, 103-104
for EPROM, 4245 resolution of, 104
propagation delay considerations, 69-70 AND gate, 316, 317f
for RAM, 4648 Architecture
Acknowledge timing, 225-226 of complex microprocessor, 333-337
ACK signal, 37 evaluation of, 12
Action codes, 172-173 Harvard, 14-15, 15f
Activate Task, 247 pipeline, 271-272
A/D converters. see Analog-todigital con- software, 129-130
verters state machine, 129-130
Address von Neumann, 1415, 15f
decoding circuits, 56f Arithmetic logic unit, 325-327
hold time, 46 Atmel
immediate, 333 AT9OS8515,llO-lll
setup time, 4648 FPSLIC, 281
Addressable memory, 327-328
Address bus Background debugging mode, 194,283
description of, 33 Background loop, 169. see also Polling
DMA, 76f, 77 lOOP(S)
multiplexing of, 35f Backplane, passive, 260
Address decoding Binary numbers, 306-308
linear, 86 BIOS, 260
partial, 86 Branching
Addressing direct, 339
direct, 337 indexed, 339
indexed, 339 indirect, 339
indirect, 339 Breakpoint
Address latch, 43 for debugging evaluations, 180-181, 192
Address latch enable signal, 33 definition of, 18
Allocate Memory, 248 logic analyzer, 180-181
Analog-to-digital converters Buffers
accuracy of, 104-105 circular trace, 178-1 79
calibration of, 105 data bus, 47,69-70
description of, 103 enabled, 86
interleaving and, 273, 274f FIFO, 211-212
internal, 105 for 1% bus, 217-218
Microchip, 105 last in, first out, 135

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