Page 364 - Embedded Microprocessor Systems Real World Design

Glossary

ADC (Analog-to-Digital Converter): An integrated circuit or subsystem that translates a
voltage or other analog value to a digital word.
Assembler: A language that directly describes machine instructions such as move data to a
register, jump to an address, add two registers, and so on. Each microprocessor has a
unique machine language and therefore a unique assembler language.
Cache: A secondary memory used to reduce the bottleneck of memory access to a fast CPU.
Data are moved from main memory into a faster cache memory and fetched from there.
When the CPU needs data that is not in the cache, it must be fetched from the main
memory.
CAN (Controller Area Network): A multinode network using a single twisted-pair cable and
capable of operating at speeds from 10 kbps to 1 Mbps. CAN originally was developed for
the automotive industry.
CISC (Complex Instruction Set Computer): A computer that includes relatively complex
instructions in the instruction set. CISC is a relative term. The instruction set of a CISC
microcontroller may be much simpler and less flexible than that of a high-performance
RISC CPU. See RISC.
Context Switch: The context of a CPU usually refers to all the internal registers, including
the stack pointer and instruction pointer. A context switch is the process of changing or
restoring the CPU context to execute a different section of code (such as an interrupt
service routine) and usually includes saving the current context.
CPLD (Complex Programmable Logic Device): A large PLD.
CPU (Central Processing Unit): Technically the computing core of a microprocessor; the
term is commonly used to refer to the microprocessor itself.
Cross Compiler/Cross Assembler: A compiler or assembler that runs on one computer but
generates object code for another family of computers. An assembler that runs on a PC
and generates code for a microcontroller is an example of cross assembly.
DAC (Digital-to-Analog Converter): An integrated circuit or subsystem that translates a digital
word to a voltage.
Daisy-chainea Interrupts An interrupt prioritizing scheme in which the priority of each
peripheral is determined by its position in the chain. Lower-priority devices may acknowl-
edge an interrupt only when no higher-priority devices are requesting an interrupt.

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