Page 367 - Embedded Microprocessor Systems Real World Design

Passive Backplane: A bus board that consists of only connectors, the interconnecting traces,
and sometimes signal terminators. The CPU in a passive backplane system plugs into the
backplane.
PC/104 Bus: A bus architecture using pass-through pin/socket connectors. Electrically
similar to the ISA bus.
Pipeline: A method of increasing processor throughput by prefetching instructions and
storing them for the CPU to execute. Pipelining takes advantage of the time that the CPU
spends executing instructions to buffer one or more additional instructions.
PLD (Programmable Logic Device): A programmable integrated circuit used to implement
logic functions.
Preemptive Scheduling: A scheduling technique in which each task is given control until it
finishes or is superceded by a higher-priority task.
PROM (Programmable Read-only Memory): A ROM that can be programmed, either by a
PROM programmer or by the target system. Once programmed, acts as a read only
memory (ROM).
Protected Mode: A memory-management mode available on some x86 family processors that
provides hardware memory protection and other features.
Race Condition: Any condition in which two signals or events that happen simultaneously
cause timing errors. The timings for hardware race conditions normally are measured in
nanoseconds or microseconds. For software events, the timing can be any window within
which the events appear simultaneous to the code.
RAM (Random Access Memory): Memory that is both readable and writable and in which
any location may be accessed at any time. Memory locations in RAM do not need to be
accessed in any specific sequence.
Real Mode: A memory management mode on x86 family processors that segments memory
into a maximum of IMB, with 64K segments, and no hardware protection against invalid
accesses.
Reentranq The ability of a section of code to be reentered without first finishing.
Reentrancy requires that variables used in the code to be stored on a stack or with some
other mechanism that prevents them from being overwritten when the code is reentered.
Reentrancy is typically needed if a routine can be interrupted and then called by the
interrupt service routine.
RISC (Reduced Instruction Set Computer): A computer that executes a simple, limited
instruction set. The idea is that a simpler instruction set can be executed very fast, making
up for the limited functionality with extreme speed. RISC is a relative term; a RISC
microcontroller may be hundreds of times slower than a CISC computer. See CISC.
ROM (Read-only Memory): A memory device that can be read from but not written to.
RTOS (Real-Time Operating System): Firmware that provides task scheduling, memory
allocation, and other services for a real-time application.
Sequential (Round-Robin) Scheduling: A scheduling technique in which tasks are given
control one at a time, in sequence, and each runs until finished.

348 Glossary