Page 366 - Embedded Microprocessor Systems Real World Design

ISA (Industry-Standard Architecture): The expansion bus and connectors used on the
original IBM AT computer.
ISR (Interrupt Service Routine): Code executed when an interrupt occurs; it handles
interrupt-specific functions.
Latency (Interrupt): The time from when an interrupt occurs to when it is serviced.
Level-Sensitive Interrupt: An interrupt that is recognized while in the active state.
Machine Iauguage: The binary ones and zeros that the microprocessor reads from memory
and executes. See Assembler.
Microcontroller: A microprocessor with internal RAM and 1/0 ports, sometimes including
ROM.
Microprocessor: An integrated circuit containing, at minimum, a central processing unit and
a means to access external memory. Microprocessors also may include internal memory,
1/0 ports, or peripherals.
p (Microsecond): One millionth of a second; seconds.
Modified Harvard Architecture: A variation on the Harvard architecture in which there is
limited ability to obtain data from the code space. Many single-chip microcontrollers use
the modified Harvard architecture.
Monitor: A program that executes on the target system and allows the engineer to examine
memory and I/O, set breakpoints, and download code. It often supports other features
as well. The term debugger is nearly synonymous with monitor and usually denotes a more
sophisticated tool with advanced features.
ms (Millisecond): One thousandth of a second seconds.

Native Development: Development of microprocessor code on the same family of CPUs as
the code will be run on. Development of code on a PC to be run on a PC is native mode
development.
Nested Interrupts: Where interrupts are structured so that a lower-priority ISR can be
interrupted by a higher-priority ISR.
NMI (Nonmaskable Interrupt): An interrupt input, available on many processors, that
cannot be masked off. If the interrupt occurs, the processor always will service it.
11s (Nanosecond): One billionth of a second; lo-' seconds.
NVRAM: A package housing a static RAM integrated circuit and a battery. The battery powers
the RAM so that it will retain its contents when external power is off.
Object Code: Code for a target system. It may be in binary or in some ASCII hex represen-
tation of the data, such as Intel or Motorola hex formats.
OW EPROM. Onetime programmable EPROM. An EPROM without the erasure window.
The OTP EPROM acts like a one-time programmable PROM but has an EPROM
structure internally.
Overflow: A condition that occurs when the result of a mathematical operation cannot be
represented by the number of bits available.

Glossary 347