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Digital-teanalog converters SRAM and, comparisons between, 49-50
accuracy of, 104-105 synchronous, 274-277
calibration of, 105 timing, 49-50
description of, 101-103 timing logic, 51f, 53
reference voltage, 103-104 -DTACK, 62
resolution of, 104 D-type latches, 321
schematic diagram of, 102f D-type registers, 321
Direct memory access. see DMA Dynamic bus sizing, 95,96f
Distributed processor systems. see also Multi-
processor systems Edge-sensitive interrupts
advantages of, 24-25 characteristics of, 151-153
description of, 24, 203 definition of, 146, 151
DMA level-sensitive interrupts and, comparison
address bus, 76f, 77 between, 151-153, 152f
for communication in multiprocessor shared, 153f
systems EEPROM
fast/slow communication problems, description of, 41
210-211,211f flash memory and, 41
principles of, 207-21 1 for 1% bus, 72
problems associated with, 208 serial, 72
scheme variations, 208, 209f write times for, 72
controllers, 77, 79, 81, 85 &bit bus, 65, 129
CPUs that support, 77 Electromagnetic interference/electromag-
definition of, 74 netic compatibility. see EMI/EMC
description of, 10 EMC;. see EMI/EMC
designing with, 75 EMI/EMC
examples of, 74 certification, 34
flyby transfer, 79 design considerations, 86-87
schematic representation of, 75f differential interfaces, 88-89
timing, 79-80, 80f emission controls, 87-88
UmT, 77, 78f ground loops, 88
Documentation radiated susceptibility, 89
schematic representation of, 2f software considerations, 127-128
software Emulators
data flow diagram, 120f, 122f cost of, 19
flowcharts, 123 debugging use, 19, 171-172, 191,
pseudocode, 123-125 192-193, 201-202
state diagram, 121-123 development language and, 132
types of, 1 drawbacks to, 19
Don't care state, 316 logic analyzer breakpoints and, 180-181
DOS packaging for, 282
real-time operating systems that emulate, ROM, 193
260-261 Engineering specifications
ROM in, 260 definition of, 4
DRAM description of, 1
address setup/hold times, 52 function of, 4, 232
built-in interface, 99-100 for multiprocessor systems, 232-233
burst mode, 273-274 EPROM. see also Flash memory
characteristics of, 48-49 access time calculations, 4245
controller ICs, 53-54 benefits of, 12
description of, 45 components of, 39
disadvantages of, 49 costs of, versus ROM, 13
refreshing of, 52-53 data hold time, 44
schematic representation of, 50f description of, 12, 39
Index 353
