Page 375 - Embedded Microprocessor Systems Real World Design

tristate, 319 selection criteria for
true/false notation, 319 development environment, 11-12
Logic gates, 316, 317f incircuit programming, 14
interfaces required, 7-8
Mailbox In, 248 interrupts needed, 9
Mask bytes, 161 1/0 pins, 5-6
Maxim MAX6576, 111-113 memory architecture, 14-15. see also
Memory Architecture
addressable, 327-328 memory requirements, 7-8
allocation blocks, 245, 2461‘ nonvolatile storage, 14
cache, 278-279 overview of, 5
dumps, 181-182 processing speed, 11-12
EPROM, 38 RAM,
7
flash. see Flash memory real-time requirements, 9-10
management of, 244-245, 284-286 ROM, 7-8
modes for addressing, 337-340 ROMability, 12-14
nonvolatile, 70-71 simple, architecture of
in real-time operating system, 244-245, addressable memory, 327-328
251 arithmetic logic unit, 325-327
requirements assessment, 7-8 branching, 329-330
shared, 160-162 conditional branching, 330
Message stackup, in FIFO buffer system, control store, 327
212 immediate data, 330
Microchip, 32f, 105, 286 opcodes, 329
Microcontrollers. see also Singlechip micro- output, 331, 333
processors program counter, 329
application-specific, 286 timing logic, 328
description of, 5-6 singlechip
digital I/O, 286 designs, 29-30
FPGA and, 281 elements of, 29-30
RAM usage limitations, 7 insufficiency of, 31
Microprocessor interface requirements, 7
categorization of, 29 multichip designs and, comparison
clock-synchronized bus, 97-99 between, 30f, 31-35
complex, architecture of, 333-337 schematic representation of, 30f
core of, 325 timebase, 29-30
environmental requirements, 16 SRAM connected to, 46f
floating-point, 8 stack, 242
internal logic of, 97 Zilog 280, 265
justification assessments, 4-5 Microwire
life cycle costs, 16-17 description of, 217-218
manufacturers of, 6 multichip designs, 106-107
multichip designs. see also Multiprocessor schematic diagram of, 71f
systems Monitor programs, for debugging, 18,
bus cycles, 34 179-180, 193
components of, 32-33 Motorola
data bus, 69, 70f 68230, 60-61
single-chip design and, comparison 68HC05,13
between, 30f, 31-35 MC68EZ328,96,99
with multiple clock inputs, 279-280 MC68HC16,95
operator training/competence, 17 memory management scheme, 286
power requirements, 15-16 timing for, 32f
programmable logic devices and, 281 Multichip designs
‘‘real’’ requirements, 17 bus cycles, 34

356 Index