Page 24 - Engineering Digital Design

PREFACE xxiii

Pulse mode approach to asynchronous FSM design (Sections 15.1 through 15.6)
Selected topics in Chapter 16
Review

EXAM #3 and/or FINAL

The choice of course content is subject to so many variables that no one course outline will
suffice even within a single institution where several instructors may teach a given course.
It is for this reason that the text is divided up into 16 relatively small chapters. This offers
the instructor somewhat more flexibility in the choice of subject matter. For example, if it is
desirable to offer a single (combined) semester course in digital design, it might be desirable
to offer both combinational and sequential (synchronous FSM) logic design. Such a course
might include the following subject areas taken from Blocks I through VI in sample course
outlines [1] and [2]:

[3] Single (Combined) Semester Course in Digital Design

Binary state terminology, and mixed-logic symbology (Sections 3.1 through 3.7)
Reading and construction of logic circuits (Section 3.8)
XOR and EQV operators and mixed-logic symbology (Section 3.9)
Laws of Boolean and XOR algebra (Sections 3.10 through 3.12)
Review

EXAM #1

Logic function representation (Sections 4.1 and 4.2)
K-map function representation and minimization, don't cares and multioutput
optimization (Sections 4.3 through 4.5)
Entered variable mapping methods and function reduction of five or more variables
(Sections 4.6, 4.7 and 4.12)
Multiplexers, decoders, priority encoders, and code converters (Sections 6.2
through 6.5)
Comparators, parity generators, and shifters or choice (Sections 6.6 through 6.8)
Adders, subtractors, and multipliers (Sections 8.1 through 8.3; Section 8.6)
Static hazards in combinational logic devices (Sections 9.1 and 9.2)
Review

EXAM #2

Heuristic development of the basic memory cells (Sections 10.1 through 10.4)
Design and analysis of flip-flops, flip-flop conversion (Sections 10.5 through 10.8)
Asynchronous overrides; setup and hold time requirements; design and analysis
of simple synchronous state machines (Sections 10.10 through 10.13)
Detection and elimination of timing defects in synchronous state machines
(Sections 11.1 through 11.3)
Synchronizing of asynchronous inputs (Section 11.4)
Initialization and reset of FSMs; debouncing circuits (Sections 11.7 and 11.8)
Shift registers and counters (Sections 12.1 through 12.3)