Page 23 - Engineering Digital Design

xxn PREFACE

Adders, subtracters, multipliers, and dividers (Section 2.6 and Subsections 2.9.1
through 2.9.5 or choice; Sections 8.1 through 8.7 or choice)
Arithmetic and logic units — ALUs (Section 8.8) — may be omitted if time-limited
Static hazards in combinational logic devices (Sections 9.1 and 9.2)
Review

EXAM #3 and/or FINAL

[2] Second-Level Course—State Machine Design and Analysis

Block IV

Introduction; models, the state diagram, and heuristic development of the basic
memory cells (Sections 10.1 through 10.4)
Design and analysis of flip-flops, flip-flop conversion; timing problems; asyn-
chronous overrides; setup and hold time requirements (Sections 10.5 through
10.11)
Design of simple synchronous finite state machines; K-map conversion; analysis
of synchronous FSMs (Sections 10.12 and 10.13)
Review

EXAM #1

Block V

Introduction; detection and elimination of timing defects in synchronous state
machines (Sections 11.1 through 11.3)
Synchronizing and stretching of asynchronous inputs; metastability; clock skew
and clock sources (Sections 11.4 through 11.6)
Initialization and reset of FSMs, and debouncing circuits (Sections 11.7 and 11.8)
Applications to the design and analysis of more complex synchronous FSMs; ASM
charts and state assignment rules; array algebraic approach to FSM design; state
minimization (Sections 11.9 through 11.12)
Review

EXAM #2

Block VI
Introduction; design of shift registers and synchronous counters; synchronous vs
asynchronous parallel loading (Sections 12.1 through 12.3)
Shift register counters and ripple counters; special purpose counters (Sections 12.4
through 12.5)
Alternative architecture — use of MUXs, decoders, PLDs, counters and shift reg-
isters; the one-hot design method (Sections 13.1 through 13.5)
The controller, data path, functional partition, and system-level design (Sections
13.6 and 13.7)
Introduction to asynchronous sequential machines — fundamental mode FSMs
(Sections 14.1 through 14.9)