Page 22 - Engineering Digital Design

PREFACE xxi

SUGGESTED TEXT USAGE

Perhaps the best advice that can be given to instructors on the use of this text is to study
the table of contents carefully and then decide what subject matter is essential to the course
under consideration. Once this is done the subject area and order of presentation will usually
become obvious. The following two course outlines are offered here as a starting point for
instructors in making decisions on course subject usage:

The Semester System
[1] First-Level Course—Combinational Logic Design

Block I

Introduction (Chapter 1)
Number systems, binary arithmetic and codes (Sections 2.1 through 2.5 or choice)
Binary state terminology, CMOS logic circuits, and mixed-logic symbology
(Sections 3.1 through 3.7)
Reading and construction of logic circuits (Section 3.8)
XOR and EQV operators and mixed-logic symbology (Section 3.9)
Laws of Boolean and XOR algebra (Sections 3.10 through 3.12)
Review

EXAM #1

Block II

Introduction; logic function representation (Sections 4.1 and 4.2)
Karnaugh map (K-map) function representation and minimization, don't cares,
and multioutput optimization (Sections 4.3 through 4.5)
Entered variable mapping methods and function reduction of five or more variables
(Sections 4.6, 4.7 and 4.12)
Introduction to minimization algorithms (Section 4.8)
Factorization and resubstitution methods (Subsections 4.9.1 and 4.9.2)
Function minimization by using XOR K-map patterns (Sections 5.1 through 5.4)
Review

EXAM #2

Block III

Introduction to combinational logic design (Section 6.1)
Multiplexers, decoders, priority encoders, and code converters (Sections 6.2
through 6.5; Section 2.10)
Magnitude comparators, parity generators and shifters (Sections 6.6 through 6.8)
Programmable logic devices — ROMs, PLAs and PALs (Sections 7.1 through 7.6)