Page 17 - Engineering Digital Design

xvi CONTENTS

13.6 System-Level Design: Controller, Data Path, and Functional Partition 649
13.6.1 Design of a Parallel-to-Serial Adder/Subtractor Control System 651
13.6.2 Design of a Stepping Motor Control System 655
13.6.3 Perspective on System-Level Design in This Text 666
13.7 Dealing with Unusually Large Controller and System-Level Designs 666
Further Reading 668
Problems 670

14. Asynchronous State Machine Design and Analysis: Basic Concepts 683
14.1 Introduction 683
14.1.1 Features of Asynchronous FSMs 684
14.1.2 Need for Asynchronous FSMs 685
14.2 The Lumped Path Delay Models for Asynchronous FSMs 685
14.3 Functional Relationships and the Stability Criteria 687
14.4 The Excitation Table for the LPD Model 688
14.5 State Diagrams, K-maps, and State Tables for Asynchronous FSMs 689
14.5.1 The Fully Documented State Diagram 689
14.5.2 Next-State and Output K-maps 690
14.5.3 State Tables 691
14.6 Design of the Basic Cells by Using the LPD Model 692
14.6.1 The Set-Dominant Basic Cell 692
14.6.2 The Reset-Dominant Basic Cell 694
14.7 Design of the Rendezvous Modules by Using the Nested Cell Model 695
14.8 Design of the RET D Flip-Flop by Using the LPD Model 698
14.9 Design of the RET JK Flip-Flop by Flip-Flop Conversion 700
14.10 Detection and Elimination of Timing Defects in Asynchronous FSMs 701
14.10.1 Endless Cycles 702
14.10.2 Races and Critical Races 703
14.10.3 Static Hazards in the NS and Output Functions 705
14.10.4 Essential Hazards in Asynchronous FSMs 711
14.10.5 Perspective on Static Hazards and E-hazards in
Asynchronous FSMs 718
14.11 Initialization and Reset of Asynchronous FSMs 719
14.12 Single-Transition-Time Machines and the Array Algebraic Approach 720
14.13 Hazard-Free Design of Fundamental Mode State Machines by Using the Nested
Cell Approach 730
14.14 One-Hot Design of Asynchronous State Machines 734
14.15 Perspective on State Code Assignments of Fundamental Mode FSMs 738
14.16 Design of Fundamental Mode FSMs by Using PLDs 740
14.17 Analysis of Fundamental Mode State Machines 741
Further Reading 758
Problems 759

15. The Pulse Mode Approach to Asynchronous FSM Design 773
15.1 Introduction 773
15.2 Pulse Mode Models and System Requirements 773
15.2.1 Choice of Memory Elements 774
15.3 Other Characteristics of Pulse Mode FSMs 777
15.4 Design Examples 779
15.5 Analysis of Pulse Mode FSMs 788