Page 13 - Engineering Digital Design

xii CONTENTS

6.2 Multiplexers 242
6.2.1 Multiplexer Design 242
6.2.2 Combinational Logic Design with MUXs 245
6.3 Decoders/Demultiplexers 248
6.3.1 Decoder Design 248
6.3.2 Combinational Logic Design with Decoders 251
6.4 Encoders 254
6.5 Code Converters 257
6.5.1 Procedure for Code Converter Design 257
6.5.2 Examples of Code Converter Design 257
6.6 Magnitude Comparators 265
6.7 Parity Generators and Error Checking Systems 273
6.8 Combinational Shifters 275
6.9 Steering Logic and Tri-State Gate Applications 278
6.10 Introduction to VHDL Description of Combinational Primitives 279
Further Reading 287
Problems 288

7. Programmable Logic Devices 295
7.1 Introduction 295
7.2 Read-Only Memories 295
7.2.1 PROM Applications 299
7.3 Programmable Logic Arrays 301
7.3.1 PLA Applications 302
7.4 Programmable Array Logic Devices 307
7.5 Mixed-Logic Inputs to and Outputs from ROMs, PLAs, and PAL Devices 310
7.6 Multiple PLD Schemes for Augmenting Input and Output Capability 312
7.7 Introduction to FPGAs and Other General-Purpose Devices 317
7.7.1 AND-OR-Invert and OR-AND-Invert Building Blocks 317
7.7.2 Actel Field Programmable Gate Arrays 319
7.7.3 Xilinx FPGAs 321
7.7.4 Other Classes of General-Purpose PLDs 328
7.8 CAD Help in Programming PLD Devices 328
Further Reading 330
Problems 331

8. Arithmetic Devices and Arithmetic Logic Units (ALUs) 335
8.1 Introduction 335
8.2 Binary Adders 335
8.2.1 The Half Adder 336
8.2.2 The Full Adder 337
8.2.3 Ripple-Carry Adders 338
8.3 Binary Subtracters 340
8.3.1 Adder/Subtractors 342
8.3.2 Sign-Bit Error Detection 343
8.4 The Carry Look-Ahead Adder 345
8.5 Multiple-Number Addition and the Carry-Save Adder 349
8.6 Multipliers 350
8.7 Parallel Dividers 353