Page 15 - Engineering Digital Design

xiv CONTENTS

10.8.4 Review of Excitation Tables 457
10.8.5 Design of Special-Purpose Flip-Flops and Latches 459
10.9 Latches and Flip-Flops with Serious Timing Problems: A Warning 461
10.10 Asynchronous Preset and Clear Overrides 463
10.11 Setup and Hold-Time Requirements of Flip-Flops 465
10.12 Design of Simple Synchronous State Machines with Edge-Triggered Flip-
Flops: Map Conversion 466
10.12.1 Design of a Three-Bit Binary Up/Down Counter: D-to-T K-map
Conversion 466
10.12.2 Design of a Sequence Recognizer: D-to-JK K-map Conversion 471
10.13 Analysis of Simple State Machines 476
10.14 VHDL Description of Simple State Machines 480
10.14.1 The VHDL Behavorial Description of the RET D Flip-flop 480
10.14.2 The VHDL Behavioral Description of a Simple FSM 481
Further Reading 482
Problems 483

11. Synchronous FSM Design Considerations and Applications 491
11.1 Introduction 491
11.2 Detection and Elimination of Output Race Glitches 491
11.2.1 ORG Analysis Procedure Involving Two Race Paths 496
11.2.2 Elimination of ORGs 496
11.3 Detection and Elimination of Static Hazards in the Output Logic 499
11.3.1 Externally Initiated Static Hazards in the Output Logic 500
11.3.2 Internally Initiated Static Hazards in the Output of Mealy and
Moore FSMs 502
11.3.3 Perspective on Static Hazards in the Output Logic of FSMs 509
11.4 Asynchronous Inputs: Rules and Caveats 510
11.4.1 Rules Associated with Asynchronous Inputs 510
11.4.2 Synchronizing the Input 511
11.4.3 Stretching and Synchronizing the Input 512
11.4.4 Metastability and the Synchronizer 514
11.5 Clock Skew 517
11.6 Clock Sources and Clock Signal Specifications 520
11.6.1 Clock-Generating Circuitry 520
11.6.2 Clock Signal Specifications 521
11.6.3 Buffering and Gating the Clock 522
11.7 Initialization and Reset of the FSM: Sanity Circuits 522
11.7.1 Sanity Circuits 523
11.8 Switch Debouncing Circuits 526
11.8.1 The Single-Pole/Single-Throw Switch 526
11.8.2 The Single-Pole/Double-Throw Switch 528
11.8.3 The Rotary Selector Switch 529
11.9 Applications to the Design of More Complex State Machines 530
11.9.1 Design Procedure 530
11.9.2 Design Example: The One- to Three-Pulse Generator 532
11.10 Algorithmic State Machine Charts and State Tables 536
11.10.1 ASM Charts 537
11.10.2 State Tables and State Assignment Rules 539
11.11 Array Algebraic Approach to Logic Design 542