Page 14 - Engineering Digital Design
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CONTENTS                                                             xiii



                       8.8  Arithmetic and Logic Units                                  357
                            8.8.1  Dedicated ALU Design Featuring R-C and CLA Capability  358
                            8.8.2  The MUX Approach to ALU Design                       363
                       8.9  Dual-Rail Systems and ALUs with Completion Signals          369
                            8.9.1  Carry Look-Ahead Configuration                       378
                       8.10 VHDL Description of Arithmetic Devices                      380
                            Further Reading                                             383
                            Problems                                                    385

                   9.  Propagation Delay and Timing Defects in Combinational Logic      391
                       9.1  Introduction                                                391
                       9.2  Static Hazards in Two-Level Combinational Logic Circuits    392
                       9.3  Detection and Elimination Hazards in Multilevel XOR-Type Functions  399
                            9.3.1  XOP and EOS Functions                                400
                            9.3.2  Methods for the Detection and Elimination of Static Hazards in
                                  Complex Multilevel XOR-type Functions                 403
                            9.3.3  General Procedure for the Detection and Elimination of Static Hazards
                                   in Complex Multilevel XOR-Type Functions             408
                            9.3.4  Detection of Dynamic Hazards in Complex Multilevel XOR-Type
                                  Functions                                             409
                       9.4  Function Hazards                                            412
                       9.5  Stuck-at Faults and the Effect of Hazard Cover on Fault Testability  412
                            Further Reading                                             413
                            Problems                                                    415

                   10. Introduction to Synchronous State Machine Design and Analysis    419
                       10.1 Introduction                                                419
                            10.1.1 A Sequence of Logic States                           420
                       10.2 Models for Sequential Machines                              421
                       10.3 The Fully Documented State Diagram: The Sum Rule            424
                       10.4 The Basic Memory Cells                                      428
                            10.4.1 The Set-Dominant Basic Cell                          428
                            10.4.2 The Reset-Dominant Basic Cell                        431
                            10.4.3 Combined Form of the Excitation Table                433
                            10.4.4 Mixed-Rail Outputs of the Basic Cells                434
                            10.4.5 Mixed-Rail Output Response of the Basic Cells        435
                       10.5 Introduction to Flip-Flops                                  436
                            10.5.1 Triggering Mechanisms                                437
                            10.5.2 Types of Flip-Flops                                  438
                            10.5.3 Hierarchical Flow Chart and Model for Flip-Flop Design  438
                       10.6 Procedure for FSM (Flip-Flop) Design and the Mapping Algorithm  440
                       10.7 The D Flip-Flops: General                                   440
                            10.7.1 TheD-Latch                                           441
                            10.7.2 The RET D Flip-Flop                                  444
                            10.7.3 The Master-Slave D Flip-Flop                         448
                       10.8 Flip-Flop Conversion: The T, JK Flip-Flops and Miscellaneous Flip-Flops  450
                            10.8.1 The T Flip-Flops and Their Design from D Flip-Flops  451
                            10.8.2 The JK Flip-Flops and Their Design from D Flip-Flops  453
                            10.8.3 Design of T and D Flip-Flops from JK Flip-Flops      455
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