Page 16 - Engineering Digital Design

CONTENTS XV

11.12 State Minimization 547
Further Reading 549
Problems 551

12. Module and Bit-Slice Devices 561
12.1 Introduction 561
12.2 Registers 561
12.2.1 The Storage (Holding) Register 562
12.2.2 The Right Shift Register with Synchronous Parallel Load 562
12.2.3 Universal Shift Registers with Synchronous Parallel Load 565
12.2.4 Universal Shift Registers with Asynchronous Parallel Load 568
12.2.5 Branching Action of a 4-Bit USR 570
12.3 Synchronous Binary Counters 572
12.3.1 Simple Divide-by-TV Binary Counters 573
12.3.2 Cascadable BCD Up-Counters 575
12.3.3 Cascadable Up/Down Binary Counters with Asynchronous
Parallel Load 579
12.3.4 Binary Up/Down Counters with Synchronous Parallel Load and True
Hold Capability 581
12.3.5 One-B it Modular Design of Parallel Loadable Up/Down Counters with
True Hold 584
12.3.6 Perspective on Parallel Loading of Counters and Registers:
Asynchronous vs Synchronous 588
12.3.7 Branching Action of a 4-Bit Parallel Loadable Up/Down Counter 589
12.4 Shift-Register Counters 590
12.4.1 Ring Counters 590
12.4.2 Twisted Ring Counters 593
12.4.3 Linear Feedback Shift Register Counters 594
12.5 Asynchronous (Ripple) Counters 600
Further Reading 605
Problems 606

13. Alternative Synchronous FSM Architectures and Systems-Level Design 613
13.1 Introduction 613
13.1.1 Choice of Components to be Considered 613
13.2 Architecture Centered around Nonregistered PLDs 614
13.2.1 Design of the One- to Three-Pulse Generator by Using a PLA 615
13.2.2 Design of the One- to Three-Pulse Generator by Using a PAL 617
13.2.3 Design of the One- to Three-Pulse Generator by Using a ROM 618
13.2.4 Design of a More Complex FSM by Using a ROM as the PLD 622
13.3 State Machine Designs Centered around a Shift Register 626
13.4 State Machine Designs Centered around a Parallel Loadable Up/Down
Counter 632
13.5 The One-Hot Design Method 636
13.5.1 Use of ASMs in One-Hot Designs 640
13.5.2 Application of the One-Hot Method to a Serial 2's Complementer 643
13.5.3 One-Hot Design of a Parallel-to-Serial Adder/Subtractor Controller 645
13.5.4 Perspective on the Use of the One-Hot Method: Logic Noise and Use
of Registered PLDs 647