Page 120 - Hardware Implementation of Finite-Field Arithmetic

Operations over GF ( p ) 103

entity binary_algorithm is
port(
x, y: in std_logic_vector(K-1 downto 0);
clk, reset, start: in std_logic;
z: out std_logic_vector(K-1 downto 0);
done: out std_logic
);
end binary_algorithm;
The VHDL architecture corresponding to the circuit of Fig. 4.4 is
the following:

long_b <= ‘0’ & b; long_a <= ‘0’ & a; long_d <= ‘0’ & d;
b_minus_a <= long_b - long_a;
sign <= b_minus_a(K);
a_minus_b <= a - b;
with sign select ba_minus_ab <= b_minus_a(K-1 downto 0)
when ‘0’,
a_minus_b when others;
with sign select ab <= a when ‘0’, b when others;
and_gates: for i in 0 to K-1 generate
p_by_d0(i) <= d(0) and p(i);
end generate;
p_by_d0(K) <= ‘0’;
d_plus_p <= long_d + p_by_d0;
divide_by_2: for i in 0 to K-1 generate
half_d(i) <= d_plus_p(i+1);
end generate;
subtractor1: subtractor port map(d, c, d_minus_c);
subtractor2: subtractor port map(c, d, c_minus_d);
with sign select dc_minus_cd <= d_minus_c when ‘0’,
c_minus_d when others;
with sign select cd <= c when ‘0’, d when others;
half_b <= ‘0’ & b(K-1 downto 1);
with sel select next_a <= p when “00”, a when “01”, ab
when others;
with sel select next_b <= y when “00”, half_b when “01”,
ba_minus_ab when others;
with sel select next_c <= ZERO when “00”, c when “01”, cd
when others;
with sel select next_d <= x when “00”, half_d when “01”,
dc_minus_cd when others;
a_equal_1 <= ‘1’ when a = ONE else ‘0’; b_0 <= b(0);
z <= c;
parallel_registers: process(clk)
begin
if clk’event and clk = ‘1’ then
if ce = ‘1’ then
a <= next_a; b <= next_b; c <= next_c; d <= next_d;
end if;
end if;
end process parallel_registers;
The complete model additionally includes a control unit.