Page 199 - Hardware Implementation of Finite-Field Arithmetic

180 Cha pte r Se v e n

Assume that the following functions
function vector_D (a,b: poly_vector) return poly_vector
function vector_E (a,b: poly_vector) return poly_vector2
computing D and E vectors given in Eq. (7.30) are available, when
poly_vector2 is a bit vector from 0 to m – 2. The new version of
Mastrovito multiplication computed in Eq. (7.29) can therefore be
given in the following algorithm, where the functions vector_D,
vector_E, and reduction_matrix_R are used, and where re: poly_vector
computes the product RE given in Eq. (7.29).

Algorithm 7.5—Mastrovito multiplication, version 2

for j in 0 .. m-1 loop c(j) := 0; re(j) := 0; end loop;
D := vector_D(a,b);
E := vector_E(a,b);
R := reduction_matrix_R(f);
for i in 0 .. m-1 loop
for j in 0 .. m-2 loop
re(i) := m2xor(re(i),m2and(R(i,j),E(j)));
end loop;
end loop;
for i in 0 .. m-1 loop c(i) := m2xor(D(i),re(i)); end loop;
An executable Ada file mastrovito_multiplication_v2.adb,
including Algorithm 7.5, is available at www.arithmetic-circuits.org.
A VHDL file mastrovito_v2_multiplier.vhd, modeling the
Mastrovito multiplication (version 2) given in Algorithm 7.5, is avail-
able at www.arithmetic-circuits.org. This model includes the process-
es genD, genE, and mastrovitoV2 that implement the generation of the
D and E vectors and the Mastrovito multiplication. The datapaths for
these components are shown in Fig. 7.3.
The entity declaration of the Mastrovito multiplier, version 2,
given in the VHDL file mastrovito_v2_multiplier.vhd is

entity mastrovito_V2_multiplication is
port (
a, b: in std_logic_vector(M-1 downto 0);
c: out std_logic_vector(M-1 downto 0)
);
end mastrovito_V2_multiplication;

The VHDL architecture is the following:
genD: process(a,b)
variable di: std_logic_vector(M-1 downto 0);
begin
for i in 0 to M-1 loop
di(i) := ‘0’;