Page 200 - Hardware Implementation of Finite-Field Arithmetic

D Vector Generation
a m–1 a 0 b 1 b 2 a 0 b m–1 b 1 a 0 b 0 a 1 b 0 a 0 a 1 b 1 a 2 b 0 a m–2 . . . . . . d 0 d 1 d 2 d m–1 R 0,m–2 R 0,1 R 0,0 R 1,m–2 R 1,1 R 1,0 ·e m–2 ·e 1 ·e 0 ·e m–2 ·e 1 ·e 0 d 0 d 1 . . . . . . c 0 c 1 Mastrovito Multiplier, second version
b 0
R 2,m–2 ·e m–2
a 1
b m–1 . . . c 2
a m–2 . . . e 0 R 2,1 ·e 1
b 2 R 2,0 ·e 0
a m–1 d 2
b 1 . . .
. . .
a m–2 Mastrovito multiplier, version 2.
b m–1 e m–3 R m–1,m–2 ·e m–2

a m–1 R m–1,1 ·e 1 . . . c m–1
E Vector Generation b m–2 a m–1 b m–1 e m–2 R m–1,0 ·e 0 d m–1 FIGURE 7.3

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