Page 197 - Hardware Implementation of Finite-Field Arithmetic

178 Cha pte r Se v e n

A VHDL file mastrovito_multiplier.vhd which models the
Mastrovito multiplication given in Algorithm 7.4 is available
at www.arithmetic-circuits.org. The corresponding entity declara-
tion is

entity mastrovito_multiplication is
port (
a, b: in std_logic_vector(M-1 downto 0);
c: out std_logic_vector(M-1 downto 0)
);
end mastrovito_multiplication;

The VHDL architecture follows:
z_matrix: process(a,z) -- Gen Z matrix
variable Zi: matrix_mastrovito;
begin
for i in 0 to M-1 loop
zi(i)(0) := a(i); zi(i)(1) := (P(0)(i) and a(M-1));
if i >= 1 then zi(i)(1) := (a(i-1) xor zi(i)(1));
end if;
for j in 2 to M-1 loop
zi(i)(j) := (P(j-1)(i) and a(M-1));
for t in 1 to j-1 loop
zi(i)(j) := (zi(i)(j) xor (P(j-1-t)(i) and
a (M-1-t)));
end loop;
if i >= j then
zi(i)(j) := (a(i-j) xor zi(i)(j));
end if;
end loop;
end loop;
Z <= zi;
end process;
mastrovito: process(b,z) --Mastrovito multiplication
variable ci: std_logic_vector(M-1 downto 0);
begin
for i in 0 to m-1 loop
ci(i) := (Z(i)(0) and b(0));
for j in 1 to m-1 loop
ci(i) := (ci(i) xor (Z(i)(j) and b(j)));
end loop;
end loop;
c <= ci;
end process;
Several works have been done using the Mastrovito scheme
outlined above for different irreducible polynomials ([HK00], [HK99],
[IHT06], [IST06], [RH04], [SK99], [ZP01]). In most of these papers, the
decomposition of the Mastrovito matrix Z in a sum of matrices is
normally used. The essence of all these works is to find an architecture
to exploit subexpression sharing [Par99 ] efficiently based on the specific