Page 193 - Hardware Implementation of Finite-Field Arithmetic

174 Cha pte r Se v e n

The VHDL architecture corresponding to the circuit of Fig. 7.2 is
the following:

register_A: process(clk)
begin
if reset = ‘1’ then aa <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if inic = ‘1’ then aa <= a;
else aa <= new_a; end if;
end if;
end process register_A;
sh_register_B: process(clk)
begin
if reset = ‘1’ then bb <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if inic = ‘1’ then bb <= b; end if;
if shift_r = ‘1’ then bb <= ‘0’ & bb(M-1 downto 1);
end if;
end if;
end process sh_register_B;
register_C: process(inic, clk)
begin
if inic = ‘1’ or reset = ‘1’ then cc <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if ce_c = ‘1’ then cc <= new_c; end if;
end if;
end process register_C;
z <= cc;
new_a(0) <= aa(m-1) and F(0);
new_a_calc: for i in 1 to M-1 generate
new_a(i) <= aa(i-1) xor (aa(m-1) and F(i));
end generate;
new_c_calc: for i in 0 to M-1 generate
new_c(i) <= cc(i) xor (aa(i) and bb(0));
end generate;

The complete model additionally includes a counter and a control
unit.

7.1.4 Matrix-Vector Multipliers
The GF(2 ) multiplication given by c(x) = a(x)b(x) mod f(x) can also be
m
described in terms of matrix-vector operations. There are mainly two
different approaches based on matrix vector operations for the
computation of a field product. As previously described the first one
is a two-step classic multiplication studied in Section 7.1.1, in which
the polynomial multiplication is performed by any method, and then
the resulting product is reduced by using a reduction matrix. In the
second approach, the polynomial multiplication and modular
reduction parts are combined in a single step by using the so-called

Mastrovito product matrix ([Mas88], [M as91]).