Page 573 - Introduction to Information Optics

558 9. Computing with Optics

9.6.3. OPTICAL LOGIC ARRAY PROCESSOR FOR PARALLEL
NSD ARITHMETIC

In earlier sections, we discussed a set of NSD arithmetic operations.
Addition and subtraction are performed at each digit position in parallel by
the same logic operations, which are thus space invariant. This property is well
suited to optical cellular architecture and, therefore, these algorithms can be
effectively mapped for optical implementation. Since all algorithms can be
executed via binary logic operations, we focus on a new implementation of
parallel optical logic. As an example, we demonstrate the parallel execution of
both addition and subtraction concurrently using the two-step carry-free
algorithm.
Various optoelectronic systems have been suggested for implementing
arithmetic-logic units. They use either linear encoding with nonlinear optical
devices, or nonlinear encoding with linear optical elements. To perform
space-variant operations, space-variant encoding and decoding must be used.
In these systems, polarization encoding is usually employed and several
subpixels are needed to represent a single digit, which increases the implemen-
tation difficulty and sacrifices the space- bandwidth product. Moreover, com-
plex logic operations can be realized in a recursive fashion by decomposing
them into simple ones. When the intermediate results are obtained, the optical
signals are converted to electronic signals, stored in the controlling electronics,
and then fed back as the input for the next iteration using SLMs. This
operation is time consuming and greatly diminishes system performance.
Recently, a novel optical logic device using electron-trapping (ET) material
has been reported, which has the advantages of high resolution, nanosecond
response time, and high sensitivity. As a result, it has been used in 3D memory,
neural networks, and optical computing systems. Here a novel method for
implementing arbitrary arithmetic and logic functions without temporal
latency is presented, and in principle, it allows the operations of any number
of variables. Based on the above algorithms and space-variant operations,
addition and subtraction can be easily realized in parallel. In this technique,
only one pixel and binary intensity values are needed for encoding each digit.
The basic principle of the ET device for logic operations was described in
Sec. 9.2.3. This technique can be extended to implement the combinational
logic involved in negabinary arithmetic. For example, the operational pro-
cedure for the logic in the two-step addition/subtraction is shown in Table 9.40,
where the overbar represents blue illumination and the underline represents
infrared illumination. The symbol xy is just an overlap of x and y. Since the
NOT operation can be realized either by negating the corresponding digits in
the SLM or by the ET device, the operational principle can be classified into
two categories, depending on whether the negation is included in the input. If
the numbers are input without negation, it is seen from Table 9.40 that the