Page 388 - Introduction to Microcontrollers Architecture, Programming, and Interfacing of The Motorola 68HC12

12.4 The 68300 Series 365

BCHG instruction that inverts a bit. Moreover, the chosen bit can be specified either by
an immediate operand or by the value in a data register. The S*** group of instructions
copies a condition code bit, or a combination of them that can be used in a branch
instruction, into a byte in memory. For example, SEQ $100 copies the Z bit into all
the bits of byte $100. The test and set instruction (TAS) is useful for some forms of
multiprocessing. It sets the condition codes as in TST, based on the initial value of a
byte, and then sets the byte's most significant bit.
Edit instructions include the standard shifts, with some modifications. All shifts that
shift the contents of a data register can be executed many times in one instruction. The
instruction ASL. W #3, DO will shift the low byte of DO three times, as in the 6812
sequence
ASLD
ASLD
ASLD
The number of shifts can be specified as an immediate operand or can be the number in a
data register. However, when shifting memory words, an instruction can shift only one
bit. Also, ROL and ROR are circular shifts of the 8- , 16-, or 32-bit numbers that do not
shift through the X bit; ROXL and ROXR are 9-, 17-, or 33-bit shifts that shift through
the X bit as the ROL and ROR instructions shift through the C bit in the 6812. EXT is a
sign extend instruction like the 6812 instruction SEX, and SWAP exchanges the low and
high words in the same data register.
Control instructions include the familiar conditional branch (B*** S), branch
(BRA.S), branch to subroutine (BSR.S), long branch (BRA.L), conditional long
branch (B*** .L), long branch to subroutine (BSR.L), jump (JMP), and jump to
subroutine (JSR) instructions, as well as the NOP, RTS, and RTE (equivalent to the
6812 RTI). The instruction RTR is like RTS, which also restores the condition codes.
Special instructions STOP and RESET permit halting the processor to wait for an
interrupt and resetting the I/O devices.
The decrement and branch group of instructions permits decrementing a counter and
simultaneously checking a condition code to exit a loop when the desired value of the
condition code is met. The condition code specified by the instruction is first tested, and
if true, the next instruction below this instruction is begun. If the condition is false, the
counter is decremented, and, if-1, the next instruction is executed; otherwise, the branch
is taken. The sequence
LI: CLR.B (A0) +
DBF DO,LI
will execute the pair of instructions n + 1 times, where n is the number in DO . This
powerful instruction allows one to construct fast program segments to move or search a
block of memory. Moreover, in the 68300 series and such short loops are detected, and,
when they occur, the two instructions are kept inside the MPU so that the opcodes need
not be fetched after the first time, so that these loops run very fast.
We now consider a few simple programs that illustrate the 68300 series instruction
set. The first is the familiar program that moves a block of 10 words from SRC to DST.
This program shows the way to specify the byte, word, or long form of most
instructions, and it shows the powerful decrement and branch instruction.