Page 393 - Introduction to Microcontrollers Architecture, Programming, and Interfacing of The Motorola 68HC12

370 Chapter 12 Other Microcontrollers

Branch instructions (bl, bla, bcl, and bcla) save the address of the next
instruction in the link register (Table 12.7). This link register can later be moved into
the program counter to return from the subroutine by a blr instruction (which can also
be conditional). If a subroutine is to call another subroutine, the contents of the link
register must be saved. While there is no hardware stack on which return addresses are
automatically saved, the programmer can implement a software stack, using any register
as a software stack pointer. The link register can be saved on this stack just after the
subroutine is entered and can be restored into the link register when the subroutine is
about to be exited by a blr instruction. It should be noted that this overhead, of saving
the return address on a stack and restoring it, is only needed if the subroutine calls
subroutines. It should be further noted that if a subroutine is called ten times, the code to
save and restore the return address is put just once in the subroutine, not in each
occurrence where the subroutine is called. Thus, even though hardware does less work in
a RISC processor than a conventional CISC processor, these tradeoffs can be justifiable.
The 500 series has a count register able to be used in decrement and count
instructions. This register can also be used like the link register to save return addresses.
To conclude this section, in Figure 12.12 we illustrate the overused inner product
subroutine, passing the parameters in registers by value. High-number registers are easy
to load and unload, using load multiple and store multiple instructions. Therefore we
assume that the vector elements V[0] and V[l] are in general registers 27 and 28, the
vector elements W[0] and W[l] are in general registers 29 and 30, and the inner product
result is left in register 31. So this example doesn't use any local variables.

12.6 The M-CORE Series

Motorola has recently introduced the M-CORE series of RISC microcontrollers. Memory
in an M-CORE processor is organized similarly to the memory in the 3xx family. This
processor has user and supervisor modes. The user mode has 16 general-purpose registers,
a program counter PC, and a carry bit C. The supervisor mode has this set, and an
alternate set, of these general purpose registers, and 13 special-purpose status and control
registers. See Figure 12.13. We will mainly discuss the user mode in this overview.
The instructions are described in Table 12.8. LD.B can load any general-purpose
register (GPR) with a byte from memory at an effective address that is the sum of a GPR
and a 4-bit unsigned constant multiplied by the data size. LD. H similarly loads a 16-bit
word, and LD. W loads a 32-bit word. These load instructions load the right bits of the
GPR, filling the other bits with zeros. Similarly, ST. B, ST. H, and ST. W store a GPR
into memory using the effective address discussed for LD.B. The LRW instruction can
load a GPR with a 32-bit word at an effective address that is the program counter PC
added to an 8-bit offset; MOV can move any GPR to any GPR; and MOVI can write a 7-
bit unsigned immediate number into a GPR. MTCR can move any GPR to any special
register, and MFCR can move any special register to any GPR. LDM permits a group of
GPRs, from a register number designated by an operand, to register r!5, using register
RO as a pointer; and STM stores such a group of registers. Similarly LDQ and STQ load
and store GPR registers r4 to r7 using any GPR as a pointer.