Page 71 - Introduction to Microcontrollers Architecture, Programming, and Interfacing of The Motorola 68HC12

48 Chapter 2 The instruction Set

A special CALL instruction permits saving and then loading a page register when
saving and then loading the program counter. That extends the addressing capability to
over 16 bits in some 6812s, such as the 'A4. The corresponding RTC instruction returns
from a subroutine called by a CALL instruction.
As noted earlier, the stack pointer is to be initialized at the beginning of a program,
with an instruction like LDS #$COO. It must be initialized before any instruction, such
as JSR or CALL, uses the stack pointer. If it is not, the RTS or RTC does not work
because the return address is "saved" in a location that is not RAM, so it is lost.
The (hardware or I/O) interrupt is very important to I/O interfacing. Basically, it is
evoked when an I/O device needs service, either to move some more data into or out of
the device or to detect an error condition. Handling an interrupt stops the program that is
running causes another program to be executed to service the interrupt and then resumes
the main program exactly where it left off. The program that services the interrupt (called
an interrupt handler or device handler) is very much like a subroutine, and an interrupt
can be thought of as an I/O device tricking the computer into executing a subroutine. An
ordinary subroutine called from an interrupt handler is called an interrupt service routine.
However, a handler or an interrupt service routine should not disturb the current program
in any way. The interrupted program should get the same result no matter if or when the
interrupt occurs.
I/O devices may request an interrupt in any memory cycle. However, the data
operator usually has bits and pieces of information scattered around in hidden registers, it
is not prepared to stop the current instruction because it doesn't know the values of these
registers. Therefore, interrupts are always recognized at the end of the current instruction,
when all the data are organized into accumulators and other registers that can be safely
saved and restored. The time from when an I/O device requests an interrupt until data that
it wants moved is moved or the error condition is reported or fixed is called the latency
time. Fast I/O devices require low latency interrupt service. The lowest latency that can
be guaranteed must exceed the duration of the longest instruction because the I/O device
could request an interrupt at the beginning of such an instruction's execution.
The SWI instruction is essentially like an interrupt. It saves all the registers as
shown in Figure 2.20c and puts the contents of $fff6, $fff7 into the program counter, to
begin an SWI handler at that address. All TRAP instructions (there are over 200 of them)
save all the registers as the SWI instruction does and put the contents of $fff8, $fff9 into
the program counter to begin a trap handler at that address, RTI pulls the contents of the
registers saved on the stack and fetches the next opcode at the address that is the returned
program counter. WAI stacks all the registers and waits for an interrupt to occur. STOP
stacks the registers and stops all the 6812 clocks to conserve power. A system reset or an
interrupt will cause the computer to resume after these instructions. Two interrupt
inhibit bits (also called an interrupt mask bit) I and X are kept in the condition code;
when they are set, interrupts are not permitted. A stop disable bit S is used to prevent
execution of the STOP instruction. BGND places the MPU in a background mode to
permit the background debug module to examine memory and registers and possibly
modify some of them. If background debugging is not enabled, BGND can be made to act
exactly like an SWI instruction.
The condition code register, accumulators, program counter, and other registers in
the controller and data operator are collectively called the machine state and are saved
whenever an interrupt occurs as shown below, resulting in the stack in Figure 2.20c.