Page 37 - Mechatronic Systems Modelling and Simulation with HDLs

26 2 PRINCIPLES OF MODELLING AND SIMULATION

simulator giving greater accuracy at a higher cost as a result of its analogue
consideration method.
For simplified applications it is often possible to put forward analytical solutions
that can be used for verification purposes. An example of this is the mechanical
deformation of a rectangular or round plate under load, which can be calcu-
lated very simply in the form of an analytical equation. The resulting elastic
line provides a starting point for the verification of the implementation of finite,
mechanical elements.

Verification based upon visual inspection and animation
Another important verification method is the visual inspection (‘eyeballing’, see
Kleijnen [193]) of the sequence of a simulation using a debugger or comparable
tool. Simulators for hardware description languages often offer the use of such
tools, which permit the representation of sequential modelling code as it is pro-
cessed. Other forms of visualisation are represented by marks in Petri nets or the
current state in state diagrams. However, visualisation can be used not only for the
evaluation of the simulation process, but also for the representation of the simula-
tion results. This is also vital because the resulting columns of figures are generally
unsuitable for providing an overview of the system behaviour. The simplest and
most widespread form is the x/y diagram, the x-axis of which is often time. In the
field of electronic circuits this is usually sufficient. However, for the evaluation of
mechanical behaviour, this is often not the case. In such cases animation procedures
facilitate a better evaluation of the simulation results and thus better verification.
It is self-evident that the animation, like any other tool to aid understanding of a
model, also makes a contribution to validation, but this is not the subject of the
present chapter.

Verification of the runtime behaviour

Occasionally tools are used that identify those parts of a model that contribute
significantly to the running time. The classic approach to this is to determine the
instruction currently being processed at regular intervals. This sampling allows
us to obtain statistical information on the frequency of the execution of instruc-
tions and modules. This is entirely sufficient for the given purpose, but does not
overload the running time of the programme under investigation. The informa-
tion extracted can be used to selectively accelerate a model, which is of decisive
importance particularly for more complex models which already have considerable
running times.

Formal verification
Formal verification will be considered here from the point of view of formal meth-
ods for the verification of digital circuits originating from microelectronics. Since