Page 200 - A Practical Guide from Design Planning to Manufacturing

Logic Design 173

the real hardware would be or is trying to simulate a set of conditions
that could never happen in the real world. The job of finding, analyz-
ing, and fixing these bugs is called design verification or validation;it
requires the skills of not only a hardware designer but of a software
designer as well.

Hardware Description Language
The complexity of modern microprocessors requires their logic design to be
extensively tested before they are manufactured. Hardware description
language (HDL) models are created to allow this simulation. Compared
with going directly to circuit design, HDL modeling dramatically reduces
design time and logic bugs. Specifying the logic at a higher level of abstrac-
tion is far easier for the designer, and simplicity reduces the chance of logic
errors. Unlike a text specification the HDL model can be tested, allowing
many logic bugs to be found and fixed before any later design steps are
attempted. HDL languages are also designed to be independent of the
manufacturing process, so that logic designs are moved easily from one
manufacturing generation to the next.
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The most commonly used forms of HDL are Verilog and VHDL (Very
High-Level HDL). HDL code is similar to general-purpose high-level pro-
gramming languages like C and Fortran, but they include the concept of
concurrency. Traditional programming languages assume that each pro-
gram instruction will be executed serially one after the other. As we have
seen in earlier discussions of microarchitecture, the processor works hard
to maintain the illusion that this is how it really operates, but in reality
there are typically many things happening simultaneously in hardware.
Unlike other program languages, HDL allows logic designs to model hard-
ware that performs multiple operations at the same time. To show the dif-
ference, Fig. 6-1 compares two pieces of code, one in C and one in Verilog.
The C code executes serially. The variable Z is calculated as the sum
of X and Y and then printed. After the value of X has been changed, vari-
able Z is printed again. In C, changing the value of variable X has no
effect on Z. In the Verilog code, an “always” block is declared to be exe-
cuted any time the variable X or Y change. The block sets Z to be the
sum of X and Y. An “initial” block then executes instructions serially in
the same way that C does.
In Verilog, changing the value of X causes the always block to be exe-
cuted again, and the value of Z to be updated. This makes output show
a different value for Z after only the variable X has been changed. The
behavior of the always block in Verilog represents the way the combi-
national logic of an adder would behave in hardware. The logic always
produces the sum of two values, and the output of the circuit will change
anytime the inputs to the circuit change.