Page 196 - A Practical Guide from Design Planning to Manufacturing

Microarchitecture 169

3. How does HyperThreading improve performance?
4. Explain Amdahl’s law in words.
5. What are some commonly used measures of processor performance?
What are their drawbacks?
6. What are the three causes of cache misses? How can each be reduced?
7. Why is cache coherency necessary? What are the four states of MESI
cache coherency protocols?
8. How can processors avoid control dependencies?
9. How can processors avoid data dependencies?
10. What are the trade-offs in choosing an instruction cache or a trace
cache?
11. [Discussion] How will data dependencies, control dependencies, and
resource conflicts affect processors trying to achieve high frequency
through deep pipelines? How will wide issue superscalar processors
be affected?
12. [Discussion] Assuming the gap between processing speed and main
memory latency continues to grow, computer performance may
become dominated by memory access time. Which microarchitec-
tural features would improve performance in this case? Which would
not? How might a computer with a processor 100 times faster than
today, but memory only twice as fast be designed differently than
current computers?

Bibliography

Amdahl, Gene. “Validity of the single-processor approach to achieving large scale computing
capabilities.” AFIPS Conference Proceedings, Atlantic City, NJ: 1967, pp. 483–485.
Hennessy, John and David Patterson. Computer Architecture: A Quantitative Approach.
3d ed., San Francisco, CA: Morgan Kaufmann, 2003.
Hilgendorf, Rolf, Gerald Heim, and Wolfgang Rosenstiel. “Evaluation of Branch-Prediction
Methods on Traces from Commercial Applications.” IBM Journal of Research and
Development, July 1999, pp. 579–593.
Hinton, Glenn, et al. “The Microarchitecture of the Pentium 4 Processor.” Intel Technology
Journal, Q1 2001, pp. 1–13.
“IA-32 Intel Architecture Optimization Reference Manual.” Intel Press, Order #248966-
011, http://www.intel.com/design/pentium4/manuals/index_new.htm.
Johnson, Mike. SuperScalar MicroProcessor Design. Englewood Cliffs, NJ: Prentice-Hall,
1991. [Johnson is a senior fellow at AMD and was an important part of the K5 and K7
design teams. This book goes through all the design choices for supporting superscalar
and out-of-order execution with tons of simulated data on effects these choices have on
performance.]
Marr, Deborah et al. “Hyper-Threading Technology Architecture and Microarchitecture.”
Intel Technology Journal, Q1 2002, pp. 4–15.
Pollack, Fred. “New Microarchitecture Challenges in the Coming Generations of CMOS
Process Technologies.” Micro32 Keynote Address, Haifa, Israel: November 1999.